MAYA-W1 series
Host-based modules with Wi-Fi and Bluetooth
Sara Moss
MAYA-W1 SIM UBX-21010495 r1
u-blox AG MAYAW161 WLAN/Bluetooth host-based multiradio module MAYA W161 XPYMAYAW161 XPYMAYAW161 mayaw161
u-blox AG MAYAW166 WLAN/Bluetooth host-based multiradio module MAYA W166 XPYMAYAW166 XPYMAYAW166 mayaw166
Instruction Manual for ublox models including: MAYAW161, XPYMAYAW161, MAYA-W1 Series Host Based Modules with WiFi and Bluetooth, MAYA-W1, MAYA-W1 Series, Host Based Modules, Host Based Modules with WiFi and Bluetooth, Modules with WiFi and Bluetooth, Modules, WiFi and Bluetooth Modules, Bluetooth Modules, WiFi Modules
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Document DEVICE REPORTGetApplicationAttachment.html?id=6188263MAYA-W1 series
Host-based modules with Wi-Fi and Bluetooth
System integration manual
Abstract
This document describes the system Integration of MAYA-W1 series short range modules with dualband Wi-Fi 4 and Bluetooth 5.1. These host-based modules are ultra-compact cost-efficient multiradio modules in the MAYA form factor, designed for a wide range of industrial applications. This module series includes variants with or without internal antenna. It includes an integrated MAC/Baseband processor and RF front end components. It can connect to a host processor through its SDIO and High-Speed UART interfaces.
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MAYA-W1 series - System integration manual
Document information
Title
MAYA-W1 series
Subtitle
Host-based modules with Wi-Fi and Bluetooth
Document type
System integration manual
Document number
UBX-21010495
Revision and date
R04
4-Jul-2022
Disclosure Restriction C2-Restricted
Document status explanation
Draft Objective Specification Advance Information Early Production Information Production Information
For functional testing. Revised and supplementary data will be published later. Target values. Revised and supplementary data will be published later. Data based on early testing. Revised and supplementary data will be published later. Data from product verification. Revised and supplementary data may be published later. Document contains the final product specification.
This document applies to the following products:
Product name MAYA-W160 MAYA-W161 MAYA-W166 MAYA-W166
Type number MAYA-W160-00B-00 MAYA-W161-00B-00 MAYA-W166-00B-00 MAYA-W166-01B-00
For information about the related hardware, software, and status of listed product types, see also
the respective data sheets [1].
u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this document. Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only permitted with the express written permission of u-blox. The information contained herein is provided "as is" and u-blox assumes no liability for its use. No warranty, either express or implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent documents, visit www.u-blox.com. Copyright © u-blox AG.
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Contents
Document information ................................................................................................................................ 2 Contents .......................................................................................................................................................... 3 1 System description...............................................................................................................................6
1.1 Overview ........................................................................................................................................................ 6 1.2 Module architecture ................................................................................................................................... 6
1.2.1 Block diagrams .................................................................................................................................... 7
2 Pin definition ........................................................................................................................................... 9
2.1 Pin attributes ............................................................................................................................................... 9 2.2 Pin assignment............................................................................................................................................ 9 2.3 Pin list ..........................................................................................................................................................10
3 Module integration............................................................................................................................. 13
3.1 Power supply interface.............................................................................................................................14 3.1.1 Digital I/O interfaces reference voltage (VIO) .............................................................................14
3.2 Antenna interfaces ...................................................................................................................................15 3.2.1 Approved antenna designs (pending) ..........................................................................................15 3.2.2 MAYA-W160, MAYA-W161, and MAYA-W166-01B ................................................................15 3.2.3 MAYA-W166-00B .............................................................................................................................16
3.3 System function interfaces ....................................................................................................................17 3.3.1 Power-up sequence ..........................................................................................................................17 3.3.2 Reset ...................................................................................................................................................18 3.3.3 Power-off sequence..........................................................................................................................18 3.3.4 Wake-up signals................................................................................................................................18 3.3.5 Configuration pins ............................................................................................................................18 3.3.6 Sleep clock..........................................................................................................................................19 3.3.7 Power states ......................................................................................................................................19
3.4 Host interfaces ..........................................................................................................................................20 3.4.1 SDIO 3.0 interface.............................................................................................................................20 3.4.2 High-speed UART interface............................................................................................................20 3.4.3 PCM/I2S - Audio interface...............................................................................................................21
3.5 Other remarks............................................................................................................................................21 3.5.1 Unused pins .......................................................................................................................................21 3.5.2 GPIO usage .........................................................................................................................................22
4 Design-in................................................................................................................................................ 23
4.1 Overview ......................................................................................................................................................23 4.2 RF interface options .................................................................................................................................23
4.2.1 Antenna design .................................................................................................................................24 4.3 Supply interfaces ......................................................................................................................................29
4.3.1 Module supply design ......................................................................................................................29 4.4 Data communication interfaces ............................................................................................................30
4.4.1 SDIO 3.0 ..............................................................................................................................................30
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4.4.2 High-speed UART interface............................................................................................................32 4.5 Other interfaces and notes .....................................................................................................................32 4.6 General high-speed layout guidelines ...................................................................................................33
4.6.1 General considerations for schematic design and PCB floor planning .................................33 4.6.2 Component placement ....................................................................................................................33 4.6.3 Layout and manufacturing .............................................................................................................33 4.7 Module footprint and paste mask .........................................................................................................34 4.8 Thermal guidelines ...................................................................................................................................35 4.9 ESD guidelines ...........................................................................................................................................36 4.10 Design-in checklists .................................................................................................................................37 4.10.1 Schematic checklist .........................................................................................................................37 4.10.2 Layout checklist ................................................................................................................................37
5 Software ................................................................................................................................................ 38
5.1 Available software packages ..................................................................................................................38 5.1.1 Open-source Linux/Android drivers ..............................................................................................38 5.1.2 MCUXpresso SDK .............................................................................................................................38
5.2 u-blox software deliverables ...................................................................................................................38 5.2.1 Yocto meta layer ...............................................................................................................................39
5.3 Software architecture ..............................................................................................................................39 5.4 Linux drivers bring-up ..............................................................................................................................40
5.4.1 Downloading Wi-Fi driver sources .................................................................................................40 5.4.2 Building the Wi-Fi driver ..................................................................................................................41 5.4.3 Downloading the firmware ..............................................................................................................41 5.4.4 Deployment to the target file system ..........................................................................................41 5.4.5 Bluetooth driver.................................................................................................................................42 5.4.6 Driver loading .....................................................................................................................................42 5.4.7 Verification .........................................................................................................................................42 5.5 Usage examples ........................................................................................................................................43 5.6 Configuration of TX power limits and energy detection ...................................................................43 5.6.1 Wi-Fi power table ..............................................................................................................................43 5.6.2 Bluetooth TX power levels...............................................................................................................46 5.6.3 Adaptivity configuration (energy detection) ...............................................................................47 5.7 Assigning MAC addresses ......................................................................................................................47
6 Handling and soldering ..................................................................................................................... 49
6.1 ESD handling precautions .......................................................................................................................49 6.2 Packaging, shipping, storage, and moisture preconditioning .........................................................49 6.3 Reflow soldering process.........................................................................................................................50
6.3.1 Cleaning ..............................................................................................................................................51 6.3.2 Other notes ........................................................................................................................................51
7 Regulatory compliance ..................................................................................................................... 52
7.1 General requirements ..............................................................................................................................52 7.2 FCC/ISED End-product regulatory compliance ..................................................................................52
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7.2.1 Referring to the u-blox FCC/ISED certification ID ......................................................................53 7.2.2 Obtaining own FCC/ISED certification ID ....................................................................................53 7.2.3 Antenna requirements ....................................................................................................................54 7.2.4 Configuration control and software security of end-products ...............................................54 7.2.5 Operating frequencies .....................................................................................................................55 7.2.6 End product labeling requirements ..............................................................................................56 7.3 CE End-product regulatory compliance ...............................................................................................57 7.3.1 Safety standard ................................................................................................................................57 7.3.2 CE Equipment classes .....................................................................................................................58 7.4 Pre-approved antennas ...........................................................................................................................58 7.4.1 Wi-Fi / Bluetooth dual band antennas ..........................................................................................58 7.4.2 Bluetooth antennas..........................................................................................................................58
8 Product testing ................................................................................................................................... 59
8.1 u-blox in-line production testing ............................................................................................................59 8.2 OEM manufacturer production test .....................................................................................................60
Appendix ....................................................................................................................................................... 61 A Glossary ................................................................................................................................................. 61 B Wi-Fi transmit output power limits .............................................................................................. 62 Related documents ................................................................................................................................... 63 Revision history .......................................................................................................................................... 64 Contact.......................................................................................................................................................... 64
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1 System description
1.1 Overview
MAYA-W1 series modules are ultra-compact, multiradio modules with Wi-Fi 4 and Bluetooth 5.1, including variants with or without an internal antenna. MAYA-W1 supports IEEE 802.11a/b/g/n Wi-Fi standards delivering up to 150 Mbps data throughput. With dual band 2.4 / 5 GHz and 40 MHz channel width, the modules can work as a station with different types of AP, as simple Access Point, in P2P communication, or a combination of these.
MAYA-W1 supports both Bluetooth BR/EDR and the full Bluetooth Low Energy 5.1 feature set, including long-range PHY. MAYA-W166-00B modules include an internal antenna with an optional sharp SAW filter. The module comes with RF calibration and MAC address available in the on-board OTP memory. The modules are developed for reliable, industrial devices and applications that demand high performance.
Radio type approvals for Europe (RED), the United States (FCC), Canada (ISED), and other country certifications (China, Japan, Taiwan, Brazil) are planned.
1.2 Module architecture
MAYA-W1 includes an NXP IW416 System-On-Chip (SoC), Wi-Fi 4 and BT 5.1 chipset, RF components, and an internal SMPS (DC/DC) converter that provides power to the internal voltage domains of the SoC.
MAYA-W1 supports a Secure Digital Input Output (SDIO) 3.0 and Universal Asynchronous Receiver Transmitter (UART) interfaces. The SDIO 3.0 interface is used for Wi-Fi communication with the Host CPU and to download MAYA-W1 firmware. Bluetooth data is transferred through the high-speed UART interface. The host interfaces must be selected through configuration pins.
A PCM/I2S interface is available to connect an external audio codec and external audio system. A 2-wire Wireless Coexistence Interface 2 (WCI-2) is also available to enable signaling between the modules and an external co-located wireless device to manage wireless medium sharing for optimal performance.
Four different module variants are supported: MAYA-W161 supports two RF pins and MAYA-W160 has two U.FL connectors for attaching an external antenna. MAYA-W166-00B is equipped with a single, embedded PCB antenna and MAYA-W166-01B with a single antenna pin.
Variant / Ordering code MAYA-W160-00B MAYA-W161-00B MAYA-W166-00B
MAYA-W166-01B
Antenna configuration
RF_ANT0: 2.4 GHz and 5 GHz Wi-Fi RF_ANT1: Bluetooth
Switched 2.4 GHz Wi-Fi, Bluetooth, and 5 GHz Wi-Fi RF_ANT1: Switched 2.4 GHz Wi-Fi, Bluetooth, and 5 GHz Wi-Fi
Table 1: Supported module configurations
Antenna type
Host interfaces
Two U.FL connectors Two antenna pins Single embedded PCB antenna
Single antenna pin
SDIO for Wi-Fi UART for Bluetooth
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1.2.1 Block diagrams
Figure 1 shows how the RF section of MAYA-W166 interfaces with the integrated Wi-Fi 4 and Bluetooth 5.1 chipset, external power management circuitry, and RF components in the NXP IW416 SoC. Switch SW1 directs either the Bluetooth or 2.4 GHz Wi-Fi signal from the SoC to the internal module antenna or antenna pin through the Diplexer and (optional) LTE bypass filter (2.4 GHz BPF). SW2 is used to suppress harmonics reflected from the 5 GHz port by disconnecting the 5 GHz path when 2.4 GHz is active. Bluetooth and 5 GHz Wi-Fi can operate simultaneously, whereas Bluetooth and 2.4 GHz Wi-Fi are time multiplexed and do not operate simultaneously.
Figure 1: Block diagram of MAYA-W166
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Figure 2 shows how the RF section of the MAYA-W160 and MAYA-161 interfaces with the integrated Wi-Fi 4 and Bluetooth 5.1 chipset, external power management circuitry, and RF components in the NXP IW416 SoC.
Similar to MAYA-W166, but in these variants the Bluetooth signal is connected directly to the Bluetooth pin (W161) or U.FL connector (W160) for use with an external antenna. Bluetooth can operate simultaneously with 2.4/5 GHz Wi-Fi.
The 2.4 GHz and 5 GHz Wi-Fi signals are multiplexed through the diplexer and are connected to the WLAN pin (W161) or U.FL connector (W160). SW1 is used to suppress harmonics reflected from the 5 GHz port by disconnecting the 5 GHz path when 2.4 GHz is active.
Figure 2: Block diagram of MAYA-161 and MAYA-160
MAYA-W1 series modules with dedicated LTE coexistence filters (2.4 GHz BPF) are available
on request. Coexistence filters are recommended for designs with co-located LTE devices operating in bands 7, 38, 40, or 41. Depending on the design, standard MAYA-W1 series modules include ceramic diplexer and LPF filters.
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2 Pin definition
2.1 Pin attributes
· FUNCTION: Pin function · PIN NAME: Name of the package pin or terminal · PIN NUMBER: Package pin numbers associated with each signal · POWER: Voltage domain that powers the pin · TYPE: Signal type description:
o I = Input o O = Output o I/O = Input and Output o D = Open drain o DS = Differential o PWR = Power o GND = Ground o PU = Internal Pull-Up o PD = Internal Pull-Down o H = High-impedance pin o RF = Radio interface · SIGNAL NAME: Signal name of the pin in the currently used mode · DESCRIPTION: Pin description and notes · ACTIVE: Pin state in Active mode · POWER DOWN: Pin state in Power Down mode
2.2 Pin assignment
Figure 3: MAYA-W1 series pin assignment (top view)
All signal pins are mounted in a land grid array (LGA) package on the bottom side of the PCB.
The RF_ANT signals are only available on MAYA-W161 modules with antenna pins.
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2.3 Pin list
No Pin name Pin type
A1
GND
GND
A2
1V8
Power
A3
SD_DAT[1] I/O
A4
SD_CLK
I
A5
SD_DAT[3] I/O
A6
VIO_SD
Power
A7
3V3
Power
A8
VIO
Power
A9
GND
GND
B1
SLP_CLK_IN I
B2
GND
GND
B3
SD_DAT[0] I/O
B4
SD_CMD I/O
B5
SD_DAT[2] I/O
B6
WCI_SOUT O
B7
3V3
Power
B8
GND
GND
B9
NC
NC
C1
NC
NC
C2
NC
NC
C4
NC
NC
C5
NC
NC
C6
WCI_SIN
I
C8
NC
NC
C9
NC
NC
D1
NC
NC
D2
NC
NC
D3
CONFIG[0] I/O
D7
NC
NC
D8
PCM_CLK I/O
D9
NC
NC
E1
NC
NC
E2
NC
NC
E3
CONFIG[1] I/O
E4
GND
E5
GND
GND GND
Description Ground 1.8 V supply SDIO data 1 SDIO clock SDIO data 3 1.8 V / 3.3 V SDIO supply 3.3 V supply 1.8 V / 2.5 V / 3.3 V I/O supply Ground Sleep clock input (optional) Ground SDIO data 0 SDIO command SDIO data 2 Coexistence serial interface 3.3 V supply Ground Reserved for VUSB Reserved for PCIe Not Connected Reserved for I2C Reserved for I2C Coexistence serial interface Not Connected Reserved for USB Reserved for PCIe Not Connected Configuration pin: CON[0]
Not Connected PCM data clock
Reserved for USB Reserved for PCIE Not Connected Configuration pin: CON[1]
Ground Ground
Alternate functions
RF control: RF_CNTL0_N GPIO mode: GPIO[6] I2S mode: I2S_BCLK RF control: RF_CNTL2_N
Power Down Tristate Tristate Tristate Tristate -
Tristate Tristate Tristate Tristate Tristate Tristate Drive low
Tristate
Drive low
-
Domain 1V8 VIO_SD VIO_SD VIO_SD VIO_SD 3V3 VIO
1V8 VIO_SD VIO_SD VIO_SD 1V8 3V3
1V8
VIO
VIO
VIO
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No Pin name Pin type Description
Alternate functions Power Down Domain
E7
BT_WAKE_ I/O
HOST
Bluetooth to host wake-up GPIO mode: GPIO[0] Drive low
VIO
E8
PCM_MCLK I/O
PCM clock signal
GPIO mode: GPIO[3] Tristate
VIO
I2S mode: I2S_CCLK
JTAG mode: JTAG_TDO
E9
PCM_DIN I/O
PCM data in
PCM mode: PCM_DOUT
Tristate
VIO
GPIO mode: GPIO[5]
I2S mode: I2S_DOUT/I2S_DIN
F1
NC
NC
Reserved for PCIe
-
F2
NC
NC
Not Connected
-
F3
RF_CNTL3_ I/O
P
RF control
Configuration pin:
Drive high
VIO
CON[5]
F4
GND
GND
Ground
-
F5
GND
GND
Ground
-
F7
WLAN_WAK I/O
E_HOST
WLAN to host wake-up
GPIO mode: GPIO[1] Tristate
VIO
Configuration pin: CON[9]
F8
PCM_SYNC I/O
PCM frame sync
GPIO mode: GPIO[7] Tristate
VIO
I2S mode: I2S_LRCLK
F9
PCM_DOUT I/O
PCM data out
PCM mode: PCM_DIN Tristate
VIO
GPIO mode: GPIO[4]
I2S mode: I2S_DOUT/I2S_DIN
Bluetooth to host wake-up
G1
NC
NC
Reserved for PCIe
-
G2
NC
NC
Not Connected
-
G3
RF_CNTL1_ I/O
P
RF control
Configuration pin:
Drive high
VIO
CON[6]
G4
NC
NC
Not Connected
-
G5
NC
NC
Not Connected
-
G7
GPIO[2]
I/O
GPIO
JTAG mode: JTAG_TDI Tristate
VIO
G8
UART_SIN I
UART serial data in
GPIO mode: GPIO[9] Tristate
VIO
G9
UART_SOU O
T
UART serial data out
GPIO mode: GPIO[10] Tristate
VIO
H1 NC
NC
Reserved for PCIe
-
H2 NC
NC
Reserved for PCIe
-
H3 NC
NC
Not Connected
-
H4 GND
GND
Ground
-
H5 GND
GND
Ground
-
H7 WLAN_RES I/O ET
WLAN reset
GPIO mode: GPIO[14] Tristate
VIO
JTAG mode: JTAG_TCK
H8 UART_CTSn I
UART CTSn
GPIO mode: GPIO[8] Drive low
VIO
Configuration pin: CON[7]
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No Pin name Pin type Description
Alternate functions Power Down
H9 UART_RTSn O
UART RTSn
GPIO mode: GPIO[11]
Configuration pin: CON[8]
Drive high
J1
NC
NC
Reserved for PCIe
-
J2
NC
NC
Reserved for PCIe
-
J3
PDn
I
Power Down Signal
-
J4
NC
NC
Not Connected
-
J5
NC
NC
Not Connected
-
J7
BT_RESET I/O
Bluetooth reset
GPIO mode: GPIO[15]
JTAG mode: JTAG_TMS
Drive high
J8
WLAN_DEV I/O
_WAKE
WLAN device wake-up
GPIO mode: GPIO[13]
UART mode: UART_DTRn
Drive high
J9
BT_DEV_W I/O
AKE
Bluetooth device wake-up
GPIO mode: GPIO[12]
UART mode: UART_DSRn
Tristate
K1
RF_ANT0 RF
WLAN I/O (only in MAYA-
-
W161)
K2
GND
GND
Ground
-
K3
GND
GND
Ground
-
K4
GND
GND
Ground
-
K5
NC
NC
Reserved for RF_ANT
-
K6
GND
GND
Ground
-
K7
GND
GND
Ground
-
K8
GND
GND
Ground
-
K9
RF_ANT1 RF
Bluetooth I/O in MAYA-
-
W161
Combined Bluetooth I/O and WLAN I/O in MAYA-W166-01B
L1
GND
GND
Ground
-
L9
GND
GND
Ground
-
M1 GND
GND
Ground
-
M2 GND
GND
Ground
-
M8 GND
GND
Ground
-
M9 GND
GND
Ground
-
Table 2: MAYA-W1 series pin description
Domain VIO
1V8 VIO VIO VIO
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3 Module integration
MAYA-W1 must be integrated into the application product together with a Host CPU system. Figure 4 shows a typical integration.
Figure 4. MAYA-W1 integration in host system
· The SDIO provides the main interface for firmware download and Wi-Fi data. The UART interface is used for handling Bluetooth data.
· Control signals for power down, reset, and host and module wake up are available to control MAYA-W1 from host CPU.
· The preferred data and communication interface between Host CPU and MAYA-W1 is set according with the instructions for Configuration pins.
· The module power supply sources the 3V3, 1V8, VIO, and VIO_SD domain pins. To match the host CPU pad voltage, VIO can be set to either 1.8 V, 2.5 V, or 3.3 V. VIO_SD can be set to 1.8 V or 3.3 V to match the SDIO interface voltage of the Host CPU.
· Select MAYA-W1 version according to the MAYA-W1 product summary [17]. · MAYA-W160 and W161 modules support dual antenna configuration for simultaneous Bluetooth
and Wi-Fi 2.4 or 5 GHz operation through the U.FL connectors or RF pins, W160 and W161. See also Block diagrams and Antenna interfaces. · MAYA-W166-00B includes an integrated antenna and MAYA-W166-01B uses a single antenna pin. In these modules, Bluetooth and Wi-Fi 2.4 GHz are time multiplexed. If requiring simultaneous Bluetooth and Wi-Fi 2.4 GHz, MAYA-W160 or MAYA-W161 must be selected · For correct operation, it is important to correctly configure MAYA-W1 with the settings and startup sequences described in the MAYA-W1 data sheet [1]. This configuration puts requirements on the power sources, timing, and assertion of PDn. · MAYA-W1 includes a PCM /I2S interface that can be used to connect a codec for Bluetooth audio. If the interface is not used, it can be omitted.
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3.1 Power supply interface
MAYA-W1 series power supply pins 3V3, 1V8, VIO, and VIO_SD pins must be sourced by a regulated DC power supply, such as an LDO or SMPS. The appropriate type for your design depends on the main power source of the application.
The DC power supply can be taken from any of the following sources:
· Switched Mode Power Supply (SMPS) · Low Drop Out (LDO) regulator
Module power up must strictly follow the defined power-up sequence. It is important to design the power management to comply with the recommended power-up sequence. The host integration and power supply sequence proposals shown in Figure 4 and Figure 5, feature a power-up mechanism that is triggered by a host GPIO and described as "MAYA-W1 Power Enable".
The current consumed through the supply pins by MAYA-W1 series modules can vary by several orders of magnitude depending on the operation mode and state. The current consumption can change from high consumption, experienced during Wi-Fi transmission at maximum RF power level in connected-mode, to low current consumption during the low power idle-mode when power saving is enabled. Regardless of the chosen DC power supply, it is crucial that it can satisfy the high peak current consumed by the module. When designing the supply circuitry for the module, a contingency of at least 20% over the stated peak current is recommended. See also Module supply design.
Domain
Allowable ripple (peak to peak)1 over DC supply
3V3 1V8 VIO_SD VIO
10-100 kHz 65 mVpk-pk 65 mV 65 mVpk-pk 65 mVpk-pk
100 kHz-1 MHz 25 mVpk-pk 25 mVpk-pk 25 mVpk-pk 25 mVpk-pk
Table 3: Summary of voltage supply requirements
>1 MHz 10 mVpk-pk 10 mVpk-pk 10 mVpk-pk 10 mVpk-pk
Current consumption, peak
750 mA 450 mA 10 mA 10 mA
Figure 5. Example of hardware-sequenced power supply
3.1.1 Digital I/O interfaces reference voltage (VIO)
The dedicated VIO pin enables integration of MAYA-W1 in either 1.8 V, 2.5 V, or 3.3 V applications without the need for level converters according to the voltage level selected. For information about the supply voltage requirements, see also the MAYA-W1 series data sheet [1].
1 Ripple measured on EVK-MAYA-W1 power connectors
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3.2 Antenna interfaces
MAYA-W1 series modules support three different antenna solutions:
· MAYA-W160 includes an integrated and external antenna through U.FL connectors, which makes this module particularly suitable for application products hosted in a metal enclosures where external antennas must be used.
· MAYA-W161 has two antenna pads that make it ideal for use with SMD antennas mounted on the main PCB.
· MAYA-W166-00B includes an integrated antenna. Utilization of the integrated antenna leverages the module pre-certification and eases integration of the module into the application.
· MAYA-W166-01B has a single antenna pad that make it ideal for use with SMD antenna mounted on the main PCB.
3.2.1 Approved antenna designs (pending)
MAYA-W1 modules come with a pre-certified antenna design that can be used to save cost and time during the certification process. To leverage this benefit, customers are required to implement an antenna layout that is fully compliant with the u-blox reference design outlined in future versions of this document2. Reference design source files are available from u-blox on request.2
For Bluetooth and Wi-Fi operation, MAYA-W1 modules have been tested and approved for use with the antennas featured in the list of Pre-approved antennas.
To avoid invalidating the compliance and pre-certification of u-blox modules with the various
regulatory bodies, use only external antennas included the list of Pre-approved antennas. u-blox modules may also be integrated with other antennas. In which case, OEM installers must certify their own designs with the respective regulatory agencies.
3.2.2 MAYA-W160, MAYA-W161, and MAYA-W166-01B
MAYA-W161 and MAYA-W166-01B are ideally used with SMD antennas mounted on the main PCB connected through the transmission lines to the RF pins.
MAYA-W160 includes two U.FL connectors to connect external antennas using coaxial cables. For proper implementation, follow the Antenna design instructions.
Follow instruction in the Antenna Integration application note [11] to implement a design compliant with the u-blox FCC certification Grant.
Pin RF_ANT0 RF_ANT1 Table 4: RF pin functions MAYA-W160 and MAYA-W161
Pin RF_ANT1 Table 5: RF pin functions MAYA-W166-01B
Function 2.4 GHz and 5 GHz Wi-Fi 2.4 GHz Bluetooth
Function Combined 2.4 GHz and 5 GHz Wi-Fi and Bluetooth
2 Reference designs are only available after certification
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3.2.3 MAYA-W166-00B
MAYA-W166-00B includes a Niche antenna that is printed on the module PCB. The antenna utilizes antenna technology from Proant AB. For proper antenna performance observe the following design considerations. If a metal enclosure is required, use a module variant with either antenna pin or U.FL connector to connect external antennas.
· To enable good antenna radiation performance, it is important to place the module on the edge of the main PCB with the antenna facing outwards.
· A ground plane extending at least 10 mm on both sides of the module is recommended. · Include a non-disruptive GND plane underneath the module with a clearance, cut out, underneath
the antenna, as shown in Figure 6. · Observe the antenna clearance shall be implemented on all layers. · To avoid degradation of the antenna characteristics, do not place physically tall or large
components closer than 10 mm to the module antenna. · To avoid any adverse impact on antenna performance, include a 5 mm clearance between the
antenna and the casing. Polycarbonate (PC) and Acrylonitrile butadiene styrene (ABS) materials have less impact on antenna performance than other types of thermoplastic. · Include plenty of stitching vias from the module ground pads to the GND plane layer. Ensure that the impedance between the module pads and ground reference is minimal. · Consider the end products use case and assembly to make sure that the antenna is not obstructed by any external item.
Figure 6: PCB artwork on main PCB top layer showing MAYA-W166-00B placement and GND clearance
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3.3 System function interfaces
3.3.1 Power-up sequence
Figure 7 shows two power-up sequences recommended for MAYA-W1 series module. During the power up of MAYA-W1 series modules, 3V3 shall be enabled first together with or followed by VIO. VIO_SD shall be supplied shortly thereafter, and later followed by 1V8.
Figure 7: Power sequence of MAYA-W1 module
In both recommended sequences, PDn is ideally held low during start up and released when the power is stable, or later when the module must be turned on. PDn is powered by the 1V8 voltage domain and is connected through a 10 k pull up resistor to 1V8.
Optionally, the PDn pad can be left unconnected so that it follows 1V8 through the pull up resistor. In which case, the power down mode is not accessible and a further full-power cycle must be made to reset the module.
During the power sequence, the internal DC/DC converter that is sourced from 3V3 must start-up before 1V8 and PDn are applied. This takes up to 1.15 ms until the internal VPA has stabilized.
Power down mode can only be entered through PDn assertion by the host. PDn must be
asserted for a minimum of 100 ms for correct reset.
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3.3.2 Reset
Although external reset is not a prerequisite for correct operation, it can be asserted by the host controller through PDn in the event of any abnormal module behavior.
MAYA-W1 series modules are reset to a default operating state by any of the following events:
· Power on (power good 90%) · PDn assert: The device is reset when the PDn input pin is < 0.2 V and transitions from low to high
A firmware download to the module is required after each reset. For information about
downloading the firmware, see also Software.
Optional independent software reset for the WLAN and Bluetooth subsystems is provided
through the WLAN_RESET and BT_RESET pins, respectively. The pins can be left open if they are not needed.
3.3.3 Power-off sequence
MAYA-W1 modules enter Power Down mode when PDn is asserted. After assertion, the power on the 3V3, 1V8, VIO, and VIO_SD supplies can be removed and the module enters the Power Off mode.
3.3.4 Wake-up signals
MAYA-W1 series modules provide wake-up input and output signals that handle the low-power modes for both Wi-Fi and Bluetooth. See also Power management.
The wake-up signals are used to exit MAYA-W1 or Host CPU from sleep modes. Wake-up signals are powered by the VIO voltage domain. WLAN_DEV_WAKE and BT_DEV_WAKE are optional, out-ofband, wake-up pins that are used to wake up the transceiver from sleep mode.
Name
I/O
WLAN_DEV_WAKE
I/O
WLAN_WAKE_HOST
I/O
BT_DEV_WAKE
I/O
BT_WAKE_HOST
I/O
Table 6: Wake-up signal definitions
Description
Host to Wi-Fi Module wake-up signal (input) / GPIO[13]
Wi-Fi Module to Host wake-up signal (output) / GPIO[1] Used as configuration pin, see also Configuration pins. Host to Bluetooth Module wake-up signal (input) / GPIO[12]
Bluetooth Module to Host wake-up signal (output) / GPIO[0] Alternatively, PCM_DOUT/GPIO[4] can be used as host wake-up signal.
3.3.5 Configuration pins
MAYA-W1 series modules support configuration pins to set specific parameters following a reset. The definition and function of these configuration pins changes immediately (~1 ms) to their initial function after reset, as shown in Table 7.
Configuration pins CON[1:0] are used to set the firmware boot options that subsequently select the interfaces used for the Wi-Fi and Bluetooth traffic. With reference to Table 7, CON[1:0] must be strapped to GND through a 50-100 k pull-down resistor to set a configuration bit to "0". No external circuitry is required to set a configuration bit to "1".
Commands and data for the Wi-Fi traffic is transferred through the SDIO bus to the module. The Bluetooth traffic uses the high-speed UART interface.
During boot-up, configuration pins CON[5:9] must be set according to the settings described in Table 7. No external circuitry is required to set the configuration, which means that these pins can left unconnected (NC). If these pins are connected, make sure that signals CON[5:9] are not pulled low by any external circuitry during boot-up. After boot, CON[5..9] revert to their main function.
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Configuration bits Pin name
CON[9]
WLAN_WAKE_HOST
CON[8]
UART_RTSn
CON[7]
UART_CTSn
CON[6]
RF_CNTL1_P
CON[5]
RF_CNTL3_P
Firmware boot options
CON[1:0]
CONFIG[1:0]
Pin number F7 H9 H8 G3 F3
CONFIG[1]: E3 CONFIG[0]: D3
Table 7: Configuration pins
Configuration settings Reserved set to 1 Reserved set to 1 Reserved set to 1 Reserved set to 1, Internal Chip pin not exposed on module Reserved set to 1
Strap value 10 Others
Wi-Fi SDIO Reserved
Bluetooth UART Reserved
3.3.6 Sleep clock
An optional external low power oscillator (LPO) for lower power operation in sleep mode can be connected to the SLP_CLK_IN pin. The external LPO must meet the requirements described in Table 9.
Name
I/O
SLP_CLK_IN
I
Description 32.768 kHz sleep clock input
Remarks
If no external sleep clock is used, leave this pin unconnected.
Table 8: External sleep clock signal description
Parameter Nominal input frequency Frequency accuracy Phase noise (@ 100 kHz) Cycle jitter Slew rate limit (10-90%) Duty cycle tolerance
LPO clock 32.768 ±250 -125 1.5 < 100 20 80
Unit kHz ppm dBc/Hz ns (RMS) ns %
Table 9: External sleep clock specification
Frequency accuracy includes temperature and aging characteristics.
3.3.7 Power states
MAYA-W1 series modules have several operation states. The power states and general guidelines for Wi-Fi and Bluetooth operations are defined in Table 10.
General status Power state
Power-down
Not Powered
Power Down
Normal operation Active Deep sleep
Description
3V3, 1V8, VIO, and VIO_SD supplies not present or below the operating range. The module is switched off.
Asserting PDn while 3V3, 1V8, VIO, and VIO_SD supplies are present powers down the module. This represents the lowest leakage mode of operation with active voltage rails. Register and memory states are not maintained in power-down mode. The module is automatically reset after exiting power-down mode, which means that the firmware must be downloaded again. If firmware is not downloaded, the device must be kept in its power-down state to reduce the leakage.
Enables TX/RX data connection with the system running at the specified power consumption.
Low-power state used in the sleep state of many power-save modes. Memory is placed in low-power retention mode.
Table 10: Description of module power states
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3.4 Host interfaces
MAYA-W1 series modules support SDIO 3.0 and high-speed UART host interfaces. This means that all Wi-Fi traffic is communicated through SDIO. By setting the appropriate boot option, the highspeed UART interface between the host and the MAYA-W1 module is configured for the Bluetooth traffic. For information about the configuration options for the host interface, see also Configuration pins.
3.4.1 SDIO 3.0 interface
MAYA-W1 series modules include a SDIO device interface that is compatible with the industrystandard SDIO 3.0 specification with a clock range of up to 100 MHz. The host controller uses the SDIO bus protocol to access the Wi-Fi function. The interface supports 4-bit SDIO transfer mode with data rates up to 50 MB/s in SDR50 or DDR50 modes. The modules also support the legacy modes, Default Speed (DS) and High-Speed (HS).
The SDIO interface voltage is set by VIO_SD to either 1.8 V or 3.3 V.
MAYA-W1 modules act as devices on the SDIO bus. Table 11 summarizes the supported bus speed modes.
Bus speed mode SDR50 DDR50 SDR25 SDR12 HS: High-Speed DS: Default Speed
Max. bus speed [MB/s] 50 50 25 12.5 25 12.5
Max. clock frequency [MHz] 100 50 50 25 50 25
VIO_SD / Signal voltage [V] 1.8 1.8 1.8 1.8 3.3 3.3
Table 11: SDIO bus speeds
MAYA includes internal 90 k pull-up resistors on the SDIO signals. Depending on the routing and trace impedance of the SDIO lines, it is recommended to connect pull-up and in-series termination resistors to these lines. See also Data communication interfaces.
Name
I/O
SD_CLK
I
SD_CMD
I/O
SD_DAT[3:0]
I/O
Description SDIO Clock input SDIO Command line SDIO Data line bits [3:0]
Table 12: SDIO signal definitions
SDIO interface pins are powered by the VIO_SD voltage domain.
Remarks
External PU required External PU required
3.4.2 High-speed UART interface
MAYA-W1 series modules support a high-speed Universal Asynchronous Receiver/Transmitter (UART) interface in compliance with the industry standard 16550 specification.
The main features of the UART interface include:
· FIFO mode permanently selected for transmit and receive operations · Two pins for transmit and receive operations · Two flow control pins (RTS/CTS) · Interrupt triggers for low-power, high-throughput operation
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· Supports standard baud rates and high throughput up to 4 Mbps. The default baud rate after reset is 115200 baud and 115200 baud after the firmware is loaded.
The UART interface operation includes:
· Bluetooth firmware upload to the module · Bluetooth data
Name
I/O
UART_SOUT
O
UART_SIN
I
UART_RTSn
O
UART_CTSn
I
Description UART TX signal UART RX signal UART RTS signal
UART CTS signal
Remarks
Connect to Host RX
Connect to Host TX
Connect to Host CTS. Used as configuration pin. See also Configuration pins.
Connect to Host RTS. Used as configuration pin. See also Configuration pins.
Table 13: UART signal description
High-Speed UART signals are powered by the VIO voltage domain.
3.4.3 PCM/I2S - Audio interface
MAYA-W1 series modules include a bi-directional 4-wire PCM digital audio interface for digital audio communication with external digital audio devices like an audio codec.
The interface supports:
· PCM master or slave mode · PCM bit width size of 8 bit or 16 bit · Up to four PCM slots with configurable bit width and start positions · PCM short frame and long frame synchronization · I2S master and slave modes for I2S, MSB, and LSB audio interfaces
PCM pins are shared with the I2S interface and can be configured to I2S mode using HCI
commands.
Name
I/O
PCM_CLK
I/O
PCM_MCLK
O
PCM_SYNC
I/O
PCM_DIN
I
PCM_DOUT
O
Description PCM clock. Alternate function: I2S clock PCM Master clock PCM frame sync. Alternate function: I2S word select PCM data in. Alternate function: I2S data in PCM data out. Alternate function: I2S data out
Table 14: PCM digital audio signal descriptions
PCM/I2S signals are powered by the VIO voltage domain.
Remarks Master output. Slave input. Optional clock used by some codecs Master output. Slave input.
3.5 Other remarks
3.5.1 Unused pins
MAYA-W1 series modules have unconnected (NC) pins that are reserved for future use. These pins must be left unconnected on the application board.
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3.5.2 GPIO usage
GPIOs are used to connect MAYA-W1 to various external devices. Table 15 shows the typical assignments for some of the GPIO pins. Other GPIO signals, described in Table 2, have not yet been assigned by the chip manufacturer. The exact function of these signals is normally dependent on the firmware releases.
GPIO GPIO[0]
GPIO[1] GPIO[4] GPIO[12] GPIO[13] GPIO[14] GPIO[15]
Module pin BT_WAKE_HOST
WLAN_WAKE_HOST PCM_DOUT BT_DEV_WAKE WLAN_DEV_WAKE WLAN_RESET BT_RESET
Function Bluetooth to host wake-up signal Can also be used to indicate the sleep mode of the module. Put to test point for debug purpose. Wi-Fi to host wake-up signal PCM data out or optional Bluetooth to host wake-up signal Host to Bluetooth Module wake-up signal Host to Wi-Fi Module wake-up signal Wi-Fi independent reset Bluetooth independent reset
Table 15: Assigned GPIO functions
Some GPIOs are used as configuration pins during boot-up. See also Configuration pins.
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4 Design-in
Follow the design guidelines stated in this chapter to optimize the integration of MAYA-W1 series modules in the final application board.
4.1 Overview
Although all application circuits must be properly designed, several aspects of the application design require special attention. A list of these points, in order of importance, follow:
· Module antenna connection: o RF_ANT0 and RF_ANT1 pins for MAYA-W161 and U.FL connectors for MAYA-W160, and RF_ANT1 for MAYA-W166-01B: Antenna circuits affect the RF compliance of all applications that include the certification schemes supported by MAYA-W1 modules. To maintain compliance and subsequent certification of the application design, it is important to observe the applicable parts of antenna schematic and layout design described in Antenna interfaces. o Internal antenna, MAYA-W166-00B: It is important to place the module on the main PCB such that the internal antenna is aligned with an outer edge of the main PCB. No GND plane or traces must be routed on any layer underneath the antenna part of the module.
· Module supply: 3V3, 1V8, VIO_SD, VIO, and GND pins. Supply circuits can affect the RF performance. It is important to observe the schematic and layout design for these supplies. See also Supply interfaces.
· High-speed interfaces: SDIO, high-speed UART pins, and PCM. High-speed interfaces are a potential source of radiated noise that can affect the regulatory compliance standards for radiated emissions. It is important to follow the schematic and layout design recommendations described in SDIO 3.0 interface and the General high-speed layout guidelines.
· System functions: PDn and Configuration pins. Careful utilization of these pins in the application design is required to guarantee that the voltage level is correctly defined during module boot. It is important to follow the pin design described in the General high-speed layout guidelines.
· Other pins: Specific signals and NC pins. Careful utilization of these pins is required to guarantee proper functionality. It is important to follow the schematic and design layout recommendations described in the General high-speed layout guidelines.
4.2 RF interface options
MAYA-W1 modules provide several RF interface options for connecting external antennas:
· MAYA-W160/MAYA-W161
o MAYA-W160 includes U.FL connectors for RF_ANT0 and RF_ANT1, whereas MAYA-W161
includes pads for these signals:
RF_ANT0 for Wi-Fi 2.4 and 5 GHz connectivity
RF_ANT1 for Bluetooth connectivity
o MAYA-W166-01B includes a RF_ANT1 pad for combined Bluetooth and Wi-Fi.
o The RF_ANT ports have a nominal characteristic impedance of 50 . For correct impedance
matching these ports must be connected to the respective antenna through a 50 U.FL
connector and coax or a transmission line depending on the type of module connector. Poor
termination of RF_ANT pins can result in degraded performance of the module.
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o Follow the requirements described in in Table 16 and Table 17 to optimize the isolation between the antennas and ensure good application performance.
· MAYA-166-00B o MAYA-166-00B includes an embedded antenna, which for optimal performance requires the module to be placed on the edge of the host PCB with the "antenna side" closest to the edge.
According to FCC regulations, the transmission line from the module antenna pin to the physical
antenna (or antenna connector on the host PCB) is considered part of the approved antenna design. Therefore, module integrators must use exactly the antenna reference design used in the module FCC type approval or certify their own design.
For instructions on how to design circuits that comply with these requirements, see also Antenna interfaces.
4.2.1 Antenna design
To optimize the radiated performance of the final product, the selection and placement of both the module and antenna must be chosen with due regard to the mechanical structure and electrical design of the product. To avoid later redesigns, it is important to decide the positioning of these components at an early phase of the product design
The compliance and subsequent certification of the RF design depends heavily on the radiating performance of the antennas.
To ensure that the RF certification of MAYA-W1 modules is extended through to the application design, carefully follow the guidelines outlined below.
· External antennas, including, linear monopole classes: o Place the module and antenna in any convenient area on the board. External antennas do not impose any restriction on where the module is placed on the PCB. o Select antennas with an optimal radiating performance in the operating bands. The radiation performance depends mainly on the antennas. o Choose RF cables that offer minimum insertion loss. Unnecessary insertion loss is introduced by low quality or long cables. Large insertion losses reduce radiation performance. o Use a high-quality 50 coaxial connector for proper PCB-to-RF-cable transition.
· Integrated antennas, such as patch-like antennas: o Internal integrated antennas impose some physical restrictions on the PCB design: - Integrated antennas excite RF currents on its counterpoise, typically the PCB ground plane of the device that becomes part of the antenna; its dimension defines the minimum frequency that can be radiated. Therefore, the ground plane can be reduced to a minimum size that should be similar to the quarter of the wavelength of the minimum frequency that has to be radiated, given that the orientation of the ground plane related to the antenna element must be considered. - Find a numerical example to estimate the physical restrictions on a PCB, where: Frequency = 2.4 GHz Wavelength = 12.5 cm Quarter wavelength = 3.5 cm in free space or 1.5 cm on a FR4 substrate PCB.
· Choose antennas with optimal radiating performance in the operating bands. Radiation performance depends on the complete product and antenna system design, including the mechanical design and usage of the product. Table 16 summarizes the requirements for the antenna RF interface.
· Make the RF isolation between the system antennas as high as possible, and the correlation between the 3D radiation patterns of the two antennas as low as possible. In general, RF separation of at least a quarter wavelength between the two antennas is required to achieve a minimum isolation and low pattern correlation. If possible, increase the separation to maximize the performance and fulfill the requirements in Table 16.
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Item Impedance Frequency Range Return Loss
Efficiency Maximum Gain
Requirements 50 nominal characteristic impedance 2400 - 2500 MHz 5150 - 5850 MHz S11 < -10 dB (VSWR < 2:1) recommended S11 < -6 dB (VSWR < 3:1) acceptable
> -1.5 dB ( > 70% ) recommended > -3.0 dB ( > 50% ) acceptable
Remarks
The impedance of the antenna RF connection must match the 50 impedance of Antenna pins.
For 802.11b/g/n/ax and Bluetooth. For 802.11a/n/ac/ax.
The Return loss or the S11, as the VSWR, refers to the amount of reflected power, measuring how well the primary antenna RF connection matches the 50 characteristic impedance of antenna pins. The impedance of the antenna termination must match as much as possible the 50 nominal impedance of antenna pins over the operating frequency range, to maximize the amount of power transferred to the antenna.
Radiation efficiency is the ratio of the radiated power to the power fed to the antenna input: the efficiency is a measure of how well an antenna receives or transmits.
To comply with regulatory agencies radiation exposure limits the maximum antenna gain must not exceed the value specified in type approval documentation.
Table 16: Summary of antenna interface requirements
Table 17 specifies additional requirements for implementing a dual antenna design.
Item Isolation (in-band)
Isolation (out-of-band)
Requirements S21 > 30 dB recommended
S21 > 35 dB recommended S21 > 30 dB acceptable
Envelope Correlation ECC < 0.1 recommended
Coefficient (ECC)
ECC < 0.5 acceptable
Remarks
The antenna-to-antenna isolation is the S21 parameter between the two antennas in the band of operation. Lower isolation might be acceptable depending on usecase scenario and performance requirements.
Out-of-band isolation is evaluated in the band of the aggressor. This ensures that the transmitting signal from the other radio is sufficiently attenuated by the receiving antenna. It also avoids any saturation and intermodulation effect on the receiver port.
The ECC parameter correlates the far field parameters between antennas in the same system. A low ECC parameter is fundamental in improving the performance of MIMO-based systems.
Table 17: Summary of Wi-Fi/Bluetooth coexistence requirements
When operating dual antennas in the same 2.4 GHz band, sufficient isolation is critical for
attaining an optimal throughput performance in Wi-Fi/Bluetooth coexistence mode.
Select antennas that provide:
· Optimal return loss (or VSWR) over all the operating frequencies. · Optimal efficiency figure over all the operating frequencies. · An appropriate gain that does not exceed the regulatory limits specified in some regulatory
country authorities like the FCC in the United States.
A useful approach for the antenna micro-strip design is to place an U.FL connector close to the embedded PCB or chip antenna. The U.FL connector only needs to be mounted on units used for verification.
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4.2.1.1 Integrated antenna design
If integrated antennas are used, the transmission line is terminated by the antennas themselves or by the antenna together with the connected coaxial cable and U.FL plug.
Consider the following the guidelines when designing the antenna:
· The antenna design process should commence at the same time as the mechanical design of the product. PCB mock-ups are useful in estimating overall efficiency and radiation path of the intended design during early development stages.
· Use antennas designed by an antenna manufacturer that provide the best possible return loss (or VSWR).
· Provide a ground plane large enough according to the related integrated antenna requirements. The ground plane of the application PCB may be reduced to a minimum size that must be similar to one quarter of wavelength of the minimum frequency that has to be radiated. The overall antenna efficiency may benefit from larger ground planes.
· Proper placement of the antenna and its surroundings is also critical for antenna performance. Avoid placing the antenna close to conductive or RF-absorbing parts, such as metal objects or ferrite sheets, as these may absorb part of the radiated power, shift the resonant antenna frequency of the antenna, or otherwise affect the antenna radiation pattern.
· Ensure that correct the installation and deployment of the antenna system, including PCB layout and matching circuitry, is done correctly. In this regard, it is recommended that you strictly follow the specific guidelines provided by the antenna manufacturer.
· Further to the custom PCB and product restrictions, antennas may also require tuning/matching to reach the target performance. It is recommended that you plan measurement and validation activities with the antenna manufacturer before releasing the end-product to manufacturing.
· The receiver section may be affected by noise sources like hi-speed digital busses. Avoid placing the antenna close to busses as DDR. Otherwise, consider taking specific countermeasures, like metal shields or ferrite sheets, to reduce the interference.
· Be aware of interaction between co-located RF systems, like LTE sidebands on 2.4 GHz band. Transmitted power may interact or disturb the performance of MAYA-W1 modules where specific LTE filter is not present.
4.2.1.2 RF transmission line design
RF transmission lines, such as those that connect from RF_ANT pins to their related antenna connectors or antenna, must be designed with a characteristic impedance of 50 .
Figure 8 shows the design options and the most important parameters for designing a transmission line on a PCB:
· Microstrip: track separated with dielectric material and coupled to a single ground plane. · Coplanar microstrip: track separated with dielectric material and coupled to both the ground plane
and side conductor. · Stripline: track separated by dielectric material and sandwiched between two parallel ground
planes.
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MAYA-W1 series - System integration manual The most common transmission line implementation is the coplanar microstrip, as shown in Figure 8.
Figure 8: Transmission line trace design
Follow these recommendations to design a 50 transmission line correctly:
· Designers must provide enough clearance from surrounding traces and ground in the same layer. In general, the trace to ground clearance should be at least twice that of the trace width. The transmission line should also be "guarded" by the ground plane area on each side.
· In the first iteration, calculate the characteristic impedance using tools provided by the layout software. Ask the PCB manufacturer to provide the final values usually calculated using dedicated software and production stack-ups. It is sometimes possible to request an impedance test coupon on side of the panel to measure the real impedance of the traces.
· Although FR-4 dielectric material can result in high losses at high frequencies, it can still be an appropriate choice for RF designs. In which case, aim to: o Minimize RF trace lengths to reduce dielectric losses. o If traces longer than few centimeters are needed, use a coaxial connector and cable to reduce losses. o For good impedance control over the PCB manufacturing process, design the stack-up with wide 50 traces with width of at least 200 µm. o Contact the PCB manufacturer for specific tolerance of controlled impedance traces. As FR-4 material exhibits poor thickness stability it gives less control of impedance over the trace width.
· For PCBs with components larger than 0402 and dielectric thickness below 200 µm, add a keep-out, that is, some clearance (void area) on the ground reference layer below any pin on the RF transmission lines. This helps to reduce the parasitic capacitance to ground.
· Route RF lines in 45 ° angle and avoid acute angles. The transmission lines width and spacing to GND must be uniform and routed as smoothly as possible.
· Add GND stitching vias around transmission lines. · Provide a sufficient number of vias on the adjacent metal layer. Include a solid metal connection
between the adjacent metal layer on the PCB stack-up to the main ground layer. · To avoid crosstalk between RF traces and Hi-impedance or analog signals, route RF transmission
lines as far from noise sources (like switching supplies and digital lines) and any other sensitive circuit. · Avoid stubs on the transmission lines. Any component on the transmission line should be placed with the connected pin located over the trace. Also avoid any unnecessary components on RF traces.
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Figure 9 shows a trace and ground design example. From top left to bottom right: layer 1 mirrored, layer 1, layer 2, layer 3, layer 4, and so on.
Figure 9: RF trace and ground design example
Figure 10 shows typical artwork implementing a coplanar microstrip on an 8-layer PCB. The trace includes, from the module pad to the PCB edge, the (module-side) coplanar microstrip section, RF connector with switch (optional), impedance matching PI network, (SMA-side) coplanar microstrip section (2), and edge mounted SMA RF connector. The ground clearance on L2 and L3 allows for a wider microstrip, which is less lossy than a narrow one. The ground clearance is especially critical in the 5 GHz band. A wider trace also has less impedance variation over PCB production batches due to the absolute tolerances in the PCB etching process.
Figure 10: Layout example showing implementation
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Figure 11 shows layout of pads for U.FL connector. Consider especially the GND clearance under the signal pad.
Figure 11: U.FL connector layout, top layer to the left and inner layer 1 to the right
4.3 Supply interfaces
4.3.1 Module supply design
Although the GND pins are internally connected, it is advisable to connect all available ground pins on the application board to solid ground with a good (low impedance) connection to external ground. This minimizes power loss, improves RF performance, and betters thermal performance.
Good connection of the module supply pins, supplied by a DC supply source, is required for accurate RF performance.
Consider the following guidelines when developing the schematic:
· All power supply pins must be connected to an appropriate DC source. · Any series component with an Equivalent Series Resistance (ESR) greater than a few m should
be avoided. The only exception to this general rule is the use of ferrite beads for DC filtering. To avoid possible instability in the DC supply, only use ferrite beads if needed. · For high-frequency filtering, additional bypass capacitors in the range of 100 nF to 1 µF are required on all supply pins. Offering low ESR/ESL resistance, a class II ceramic capacitor with an X7R or X5R dielectric is well suited for this purpose. Bypass capacitors of a smaller size can be chosen to minimize ESL (Equivalent Series Inductance) in the manufacturing process. The capacitor should be placed as close as possible to the module supply pin. · To help filter current spikes from the RF section and avoid ground bounce, a minimum bulk capacitance of 10 µF should be applied to the 1V8 and 3V3 rails (optionally on VIO_SD and VIO) and placed close to the module supply pins. Offering low ESR/ESL resistance, a class II ceramic capacitor with an X7R or X5R dielectric is well suited for this purpose. Special care should be taken in the selection of X5R/X7R dielectrics due to capacitance derating versus DC bias voltage.
4.3.1.1 Guidelines for supply circuit design using an SMPS
When choosing between an SMPS or LDO to supply the modules, it is advisable to consider the acceptable power and thermal dissipation of the application product.
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A Switched Mode Power Supply (SMPS) is generally recommended for converting the main supply to the module supply when the voltage difference is relatively high. In these circumstances, the use of an SMPS dissipate less power and subsequently generates less power dissipation and heat than an LDO. See also Regulated DC power supply.
By contrast, an LDO is generally simpler to use and does not generate the amount of noise an SMPS might. See also Guidelines for supply circuit design using a Low Drop-Out (LDO) linear regulator.
The characteristics of the SMPS should meet the following prerequisites to comply with the module requirements described in Table 3.
· Power capability: The regulator, together with any additional filter in front of the module, must be capable of providing a voltage within the specified operating range. It must also be capable of delivering the specified peak current.
· Low output ripple: The peak-to-peak ripple voltage of the switching regulator must not exceed the specified limits. This requirement is appliable to both the voltage ripple generated by the SMPS at operating frequency and the high-frequency noise generated by power switching.
· PWM/PFM mode operation: It is advisable to select regulators that support a fixed Pulse Width Modulation (PWM) mode. Pulse Frequency Modulation (PFM) mode typically exhibits higher ripple and can affect RF performance. If power consumption is not a primary concern, PFM/PWM mode transitions should be avoided in favor of fixed PWM operation to reduce the peak-to-peak noise on voltage rails. Switching regulators with mixed PWM/PFM mode can be used provided that the PFM/PWM modes and transition between modes complies with the requirements.
4.3.1.2 Guidelines for supply circuit design using a LDO linear regulator
The use of a linear regulator is appropriate when the difference between the available supply rail and the module supply is relatively low. Linear regulators can also be considered for powering 1.8 V domains particularly those having low current requirements and those cascaded from an SMPSgenerated low voltage rail.
The characteristics of the Low Drop-Out (LDO) linear regulator used to power the voltage rails must meet the following prerequisites to comply with the requirements summarized in Table 3.
· Power capabilities: The LDO linear regulator must be able to provide a voltage within the specified operating range. It must also be capable of withstanding and delivering the maximum specified peak current while in "connected mode".
· Power dissipation: The power handling capability of the LDO linear regulator must be checked to limit its junction temperature to the maximum rated operating range. The worst-case junction temperature can be estimated as shown below: , = ( - ) + Where: is the junction-to-ambient thermal resistance of the LDO package3, is the current consumption of the given voltage rail in continuous TX/RX mode and is the maximum operating temperature of the end product inside the housing.
4.4 Data communication interfaces
4.4.1 SDIO 3.0
The SDIO 3.0 bus in MAYA-W1 series modules can support a clock frequency up to 100 MHz, which means that special care must be taken to guarantee signal integrity and minimize electromagnetic interference (EMI) issues. The signals should be routed with a single-ended impedance of 50 .
3 Thermal dissipation capability reported on datasheets is usually tested on a reference board with adequate copper area (see also JESD51 [10]). Junction temperature on a typical PCB can be higher than the estimated value due to the limited space to dissipate the heat. Thermal reliefs on pads also affect the capability of a device to dissipate heat.
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It is advisable to route all signals in the bus so that they have the same length and the appropriate grounding in the surrounding layers. The total bus length should be kept to a minimum. To minimize crosstalk with other parts of the circuit, the layout of the SDIO bus should be designed with adequate isolation between the signals, clock, and surrounding busses/traces.
Implement an undisrupted return-current path in close vicinity to the signal traces. Figure 12 shows an optional application schematic for the SDIO bus in MAYA-W1, while Table 18 summarizes the electrical requirements of the bus. Even though MAYA-W1 includes on chip Pull-up resistors it is advisable to add external ones for optimum pull-up to match routing and host CPU impedance.
Figure 12: SDIO application schematic
A small value capacitor in the range of a few pF to GND could be considered for SDIO_CLK as
an EMI debug option and signal termination. This capacitor should be placed as close as possible to the MAYA-W1 clock input pin and can be assembled only for EMI purpose. The capacitor value adds to total line capacitance and must not exceed total allowed capacitance to avoid violating clock rise and fall timing specifications.
Signal group CLK, CMD, DAT[0:3] CLK, CMD, DAT[0:3] DAT[0:3] CMD CLK, CMD, DAT[0:3] CLK, CMD, DAT[0:3] CMD, DAT[0:3] CLK CMD, DAT[0:3]
Parameter Single ended impedance, 0 Impedance control Pull-Up range, Rdat Pull-Up range, Rcmd Series termination (Host side), Rterm4 Bus length5 Bus skew length mismatch to CLK Center to center CLK to other SDIO signals6 Center to center between signals11
Table 18: SDIO bus requirements
Min.
0 - 10% 10 10 0
Typ. 50
0 47 10 0
-3 4*W 3*W
Max.
0 + 10% 100 50
100 +3
Unit k k mm mm
4 Series termination values larger than typical recommended only for addressing EMI issues 5 Routing should minimize the total bus length. 6 To accommodate BGA escape, center-to-center spacing requirements can be ignored for up to 10 mm of routed length.
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4.4.2 High-speed UART interface
The high-speed UART interface for the MAYA-W1 complies with the HCI UART Transport layer and uses the settings shown in Table 19.
UART Settings Baud rate default after reset Baud rate default after firmware load Data bits Parity bit Stop bit Flow Control
115200 baud 3000000 baud 8 No parity 1 stop bit RTS/CTS
Table 19: HCI UART transport layer settings
RTS/CTS flow control is used to prevent temporary UART buffer overrun. · If CTS is 1 the Host/Host Controller is allowed to send. · If CTS is 0 the Host/Host Controller is not allowed to send.
The use of hardware flow control with RTS/CTS is mandatory.
Baud rate 1200 2400 4800 9600 19200
38400 57600 76800 115200 230400
460800 500000 921600 1000000 1382400
1500000 1843200 2000000 2100000 2764800
3000000
Table 20: Possible baud rates for the UART interface
After a hardware reset, the UART interface is configured for 115200 baud. After loading the firmware, the baud rate is set to 3000000 baud. A host application can configure the desired baud rate for the UART interface with the vendor specific HCI command HCI_CMD_MARVELL_UART_BAUD.
HCI command syntax using hcitool:
hcitool i hci0 cmd 0x3F 0x0009 <4-byte value for baud rate>
In the following example, the baud rate is set to 3000000 baud.
$ hcitool i hci0 cmd 0x3F 0x0009 0xC0 0xC6 0x2D 0x00 < HCI Command: ogf 0x3f, ocf 0x0009, plen 4
C0 C6 2D 00 > HCI Event: 0x0e plen 4
01 7A 0C 00
The command complete event is transmitted to the host at the old baud rate. Once the host receives it, it can switch to the new baud rate and should wait for 5 ms or more before sending the next command.
4.5 Other interfaces and notes
All pins have internal keeper resistors; leave un-used pins open.
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4.6 General high-speed layout guidelines
These guidelines describe best practices for the layout of all high-speed busses on MAYA-W1. Designers should prioritize the layout of higher speed busses. Low frequency signals, other than those with high-impedance traces, are generally not critical to the layout.
Low frequency signals with high-impedance traces (such as signals driven by weak pull resistors)
may be affected by crosstalk. For these high impedance traces, a supplementary isolation of 4*W from other busses is recommended.
4.6.1 General considerations for schematic design and PCB floor planning
· Verify which signal bus requires termination and add appropriate series resistor terminations to the schematics.
· Carefully consider the placement of the module with respect to the antenna position and host processor; minimize RF trace length first and then the SDIO bus length.
· SDIO bus routing must aim to keep layer-to-layer transition to a minimum. · Verify the allowable stack-ups, and the controlled impedance dimensioning for antenna traces and
busses, with the PCB manufacturer. · Verify that the power supply design and power sequence are compliant with the MAYA-W1
specifications described in System function interfaces.
4.6.2 Component placement
· Accessory parts like bypass capacitors must be placed as close as possible to the module to improve filtering capability. Prioritize placing the smallest capacitors close to module pins.
· Do not place components close to the antenna area. Follow the recommendations of the antenna manufacturer to determine distance of the antenna in relation to other parts of the system. Designers should also maximize the distance of the antenna to High-frequency busses, like DDRs and related components. Alternatively, consider an optional metal shield to reduce interferences that might otherwise be picked up by the antenna and subsequently reduce module sensitivity.
4.6.3 Layout and manufacturing
· Avoid stubs on high-speed signals. Test points or component pads should be placed over the PCB trace.
· Verify the recommended maximum signal skew for differential pairs and length matching of buses.
· Minimize the routing length; longer traces degrade signal performance. Ensure that maximum allowable length for high-speed busses is not exceeded.
· Ensure to track your impedance matched traces. Consult early with your PCB manufacturer for proper stack-up definition.
· RF, analog, and digital sections should have dedicated and clearly separated areas on the board. · No digital routing is allowed in the GND reference plane area of RF traces (ANT pins and Antenna). · Designers are strongly recommended to avoid digital routing beneath all layers of RF traces. · Ground cuts or separation are not allowed below the module. · As a first priority, minimize the length of the RF traces. Then, minimize bus length to reduce
potential EMI issues related to the radiation of digital busses. · All traces (Including low speed or DC traces) must couple with a reference plane (GND or power).
High-speed busses should be referenced to the ground plane. If designers need to change the ground reference, an adequate number of GND vias must be added in the area of transition. This facilitates a low-impedance path between the two GND layers for the return current.
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· Hi-speed busses are not allowed to change reference plane. If a change to the reference plane is unavoidable, some capacitors should be added in the area to provide a low impedance return path through the various reference planes.
· Trace routing should maintain a distance that is greater than 3*W from the edge of the ground plane routing.
· Power planes should maintain a safe distance from the edge of the PCB. The distance must be sufficient to route a ground ring around the PCB, and the ground ring must then be stitched to other layers through vias.
· Route the power supply in low impedance power planes. If you choose to route the power supply with traces, do not route loop structures.
The heat dissipation during continuous transmission at maximum power can significantly raise
the temperature of application baseboards under MAYA-W1 series modules. Avoid placing temperature sensitive devices close to the module and provide these devices with sufficient grounding to transfer generated heat to the PCB.
4.7 Module footprint and paste mask
Figure 13: Recommended footprint for MAYA-W1, bottom view
Figure 13 shows the pin layout of MAYA-W1 series modules. The ground clearance, marked as "RF KEEP-OUT AREA", is only required for the MAYA-W166-00B variant with an internal antenna. The proposed land pattern layout complements the pin layout of the module. Both Solder Mask Defined (SMD) and Non Solder Mask Defined (NSMD) pins can be used with adherence to the following considerations:
· All pins should be Non-Solder Mask Defined (NSMD) · To help with the dissipation of the heat generated by the module, GND pads must have good
thermal bonding to PCB ground planes.
The suggested stencil layout for the MAYA-W1 module should follow the copper pad layout, as shown in Figure 13.
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4.8 Thermal guidelines
MAYA-W1 series modules are designed to operate from -40 °C to +85 °C at an ambient temperature inside the enclosure box. The board generates heat during high loads that must be dissipated to sustain the lifetime of the components.
The improvement of thermal dissipation in the module decreases its internal temperature and consequently increases the long-term reliability of device applications operating at high ambient temperatures.
For best performance, layouts should adhere to the following guidelines:
· Vias specification for ground filling: 300/600, with no thermal reliefs allowed on vias. · Ground via densities under the module: 50 /2; thermal vias can be placed in gaps between
the thermal pads of the module. · Minimum layer count and copper thickness: 4 , 35 . · Minimum board size: 5570 . · To optimize the heat flow from the module, power planes and signal traces should not cross the
layers beneath the module.
These recommendations facilitate a design that is capable of achieving a thermal characterization parameter of = 18.2 °/ for MAYA-W160 and MAYA-W161 and = 19.4 °/ for MAYA-W166, where, refers to the junction between the module and the bottom side of the main PCB characterization parameter.
Use the following hardware techniques to further improve thermal dissipation in the module and optimize its performance in customer applications:
· Maximize the return loss of the antenna to reduce reflected RF power to the module. · Improve the efficiency of any component that generates heat, including power supplies and
processor, by dissipating it evenly throughout the application device. · Provide sufficient ventilation in the mechanical enclosure of the application. · For continuous operation at high temperatures, particularly in high-power density applications or
smaller PCB sizes, include a heat sink on the bottom side of the main PCB. The heat sink is best connected using electrically insulated / high thermal conductivity adhesive7.
7 Typically not required.
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4.9 ESD guidelines
MAYA-W1 modules are manufactured using a highly automated process, which complies with IEC61340-5-1 [6] (STM5.2-1999 Class M1 devices) standard. Customer on-site manufacturing processes that satisfy the basic ESD control program are sufficient to comply with the necessary precautions8 for handling the modules.
Table 21 describes the target ESD ratings of the MAYA-W1 pins subject to module qualification.
Applicability Human Body Model (HBM), ANSA/ESDA/JEDEC JS-001-2014. Charged Device Model (CDM), JESD22-C101.
Immunity level ±2000 ±500
Unit V V
Table 21: ESD immunity rating for pins of the MAYA-W1 module
In compliance with the following European regulations, designers must implement proper protection measures against ESD events on any pin exposed to end users:
· ESD testing standard CENELEC EN 61000-4-2 [4] · Radio equipment standard ETSI EN 301 489-1 [5]
The minimum requirements as per these European regulations are summarized in Table 22.
Application
All exposed surfaces of the radio equipment and any ancillary equipment in the end product.
Category Immunity level
Contact 4 kV discharge
Air
8 kV
discharge
Table 22: Minimum ESD immunity requirements based on EN 61000-4-2
Compliance with the protection levels specified in EN 61000-4-2 [4] are fulfilled by including proper ESD protection in parallel to any susceptible trace that is close to areas accessible to end users.
Special care should be taken with the RF_ANT pins that must be protected by choosing an ESD
absorber with adequate parasitic capacitance. For 5 GHz operation, a protection with maximum
internal capacitance of 0.1 pF is advised.
8 Minimum ESD protection level for safe handling is specified in JEDEC JEP155 (HBM) and JEP157 (CDM) for ±500 V and ±250 V respectively.
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4.10 Design-in checklists
4.10.1 Schematic checklist
MAYA-W1 module pins have been properly numbered and designated in the schematic (including
thermal pins). See Pin list.
Power supply design complies with the voltage supply requirements in Table 3 and the power
supply requirements described in the MAYA-W1 data sheet [1].
The Power-up sequence has been properly implemented Adequate bypassing has been included in front of each power pin. See Power-up sequence. Each signal group is consistent with its own power rail supply or proper signal translation has been
provided. See Pin list.
Configuration pins are properly set at bootstrap. See Configuration pins. SDIO bus includes series resistors and pull-ups, if needed. See also Figure 11 and SDIO 3.0. Unused pins are properly terminated. See Unused pins. A pi-filter is provided in front of each antenna for final matching. High-speed UART interface. Additional RF co-location filters have been considered in the design. See Block diagrams.
4.10.2 Layout checklist
PCB stack-up and controlled impedance traces follow the recommendations given by the PCB
manufacturer. See RF transmission line design.
All pins are properly connected, and the footprint follows u-blox pin design recommendations. See
Module footprint and paste mask.
Proper clearance has been provided between the RF and digital sections of the design. See Layout
and manufacturing.
Proper isolation has been provided between antennas (RF co-location, diversity, or multi-antenna
design). See Layout and manufacturing.
Bypass capacitors have been placed close to the module. See Component placement. Low impedance power path has been provided to the module. See Component placement. Controlled impedance traces have been properly implemented in the layout (both RF and digital)
and the recommendations provided by the PCB manufacturer have been followed. See RF transmission line design and Component placement.
50 RF traces and connectors follow the rules described in Antenna interfaces. Antenna integration has been reviewed by the antenna manufacturer. Proper grounding has been provided to the module for the low impedance return path and heat
sink. See Layout and manufacturing.
Reference plane skipping has been minimized for high frequency busses. See Layout and
manufacturing.
All traces and planes are routed inside the area defined by the main ground plane. See Layout and
manufacturing
u-blox has reviewed and approved the PCB9.
9 This is applicable only for end-products based on u-blox reference designs.
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5 Software
This chapter describes the available software options for MAYA-W1 series modules, which are based on the NXP IW416 chipset. The drivers and firmware required to operate MAYA-W1 series modules are developed by NXP and are pre-integrated into the Linux BSP for NXP i.MX processors [12] and the MCUXpresso SDK for NXP MCU devices [13].
5.1 Available software packages
Wi-Fi and Bluetooth drivers for MAYA-W1 series modules are pre-integrated into the software images for NXP based host platforms. The documentation for the software releases from NXP contains WiFi and Bluetooth release notes and a list of supported software features. The driver source code is provided free of charge as open source under NXP licensing terms.
As open-source code, the Wi-Fi and Bluetooth drivers can be integrated or ported to other non-
NXP based host platforms.
5.1.1 Open-source Linux/Android drivers
The Wi-Fi driver and firmware for MAYA-W1 series modules are integrated into the Linux BSP for NXP i.MX processors. Yocto recipes for the driver and firmware, that can be used to develop custom Linuxbased systems, are part of the NXP i.MX Linux BSP.
The latest version of the driver source code and Wi-Fi/Bluetooth firmware are available from the following open-source repositories:
· Wi-Fi driver:
https://source.codeaurora.org/external/imx/mwifiex/
· Firmware:
https://github.com/NXP/imx-firmware/
· Yocto Recipes: https://source.codeaurora.org/external/imx/meta-imx/
o ./meta-bsp/recipes-connectivity/nxp-wlan-sdk
o ./meta-bsp/recipes-kernel/kernel-modules/kernel-module-nxp89xx.bb
o ./meta-bsp/recipes-kernel/linux-firmware/linux-firmware_%.bbappend
Use the repository branches matching to the latest Linux BSP release version. As of writing,
this is release 5.15.32_2.0.0.
5.1.2 MCUXpresso SDK
The MCUXpresso SDK is a comprehensive software enablement package for MCU devices from NXP. It includes production-grade software with optionally integrated real-time operation systems (RTOS), integrated enabling software technologies (stacks and middleware), reference software, and more. The SDK includes the Wi-Fi and Bluetooth drivers and firmware for MAYA-W1 series modules for supported NXP MCUs. MCUXpresso Wi-Fi/Bluetooth support for NXP IW416 chipset in MAYA-W1 is currently available for FreeRTOSTM real-time operation system.
5.2 u-blox software deliverables
The following additional software deliverables are provided by u-blox for MAYA-W1 series modules: · A Yocto/OpenEmbedded meta layer, which includes recipes for related development tools. For
more information about the Yocto layer, see also Yocto meta layer.
For the latest MAYA-W1 series software deliverables, contact your local support team.
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5.2.1 Yocto meta layer
Yocto is an open-source project aimed at helping the development of custom Linux-based systems for embedded products. It provides a complete development environment with tools, documentation, and metadata like recipes, classes, and configuration. Yocto is based on the OpenEmbedded build system.
A Yocto/OpenEmbedded meta layer "meta-ublox-modules" is provided by u-blox for all host-based modules. This layer is used in Yocto projects to build the image for most host platforms that run Linux kernels. It contains the recipes used to build the Linux drivers, support tools, and any configuration files that are needed to operate the modules.
Item Build recipe Patches Calibration files Output power configuration Modprobe rules Manufacturing package recipes
Description
Includes all the instructions to extract, compile and install the drivers, firmware and tools in the root file system of the host system image.
Used to fix bugs in u-blox-distributed drivers seen either locally or reported by the vendor.
Calibration files, provided by u-blox, used while loading the driver. These files store the tuning parameters needed for RF parts present in the module, like the crystal.
RF power specific files for the different bands, rates and countries are stored in configuration files provided by u-blox.
Configuration files for the modprobe utility used to store the driver load parameters.
Includes different recipes for building the manufacturing tools. These recipes are used in production and RF-related tests.
Table 23: Content of the Yocto layer
Calibration files are needed for the modules during the prototype stage of development. After
prototyping, all required calibrations are programmed into the OTP on the module.
Further information about the Yocto layer and how to integrate it into the development
environment is provided in the README files of the meta layer.
5.3 Software architecture
From the software point of view, host-based MAYA-W1 series modules contain only on-board OTP memory with calibration parameters and MAC addresses. Consequently, the modules require a hostside driver and device firmware to run. At startup and at every reset or power cycle, the host driver needs to download the firmware binary file to the module. The firmware binary file is typically a "combo" firmware, which comprises the Wi-Fi and Bluetooth firmware images, and it is downloaded to the module by the Wi-Fi driver through the Wi-Fi host interface.
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Figure 14 shows the basic architecture of the Linux open source, Wi-Fi driver (mxm_mwifiex), which is a unified driver for all supported NXP Wi-Fi chipsets. The driver allows simple migration and forward compatibility with future devices. Driver sources can be used or ported for other non-NXP host platforms. Bluetooth uses the Linux BlueZ host stack through the HCI UART interface of the module, but other stacks can also be supported.
Figure 14: Basic Wi-Fi and Bluetooth driver architecture
The host driver interfaces the lower-layer bus drivers with the upper-layer protocol stacks of the operating system. The Wi-Fi driver uses the TCP/IP stack from the Linux kernel for data transmission, and the cfg80211 subsystem in the kernel is used for configuration and control. The hci_uart driver from the Linux kernel and BlueZ host stack are used for the Bluetooth part.
5.4 Linux drivers bring-up
The following steps explain how to download, build, and load the Linux open source drivers for the MAYA-W1 series modules.
5.4.1 Downloading Wi-Fi driver sources
Download the Wi-Fi driver sources from the Git repository:
$ git clone http://source.codeaurora.org/external/imx/mwifiex $ cd mwifiex/ $ git checkout lf-5.15.5_1.0.0
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5.4.2 Building the Wi-Fi driver
A (cross-)toolchain for the target system is required and configured kernel sources must be available and prepared for building external kernel modules. Make sure that CONFIG_CFG80211 is enabled in the kernel configuration. To prepare fresh kernel sources, configure the kernel and run make modules_prepare in the kernel source directory. Before building the driver, make sure that the NXP chipset (IW416, formerly 88W8978) used in the MAYA-W1 module is enabled in the driver Makefile and disable i.MX support on non-NXP platforms:
CONFIG_SD8978=y CONFIG_IMX_SUPPORT=n
Environment variables ARCH, CROSS_COMPILE, and KERNELDIR must be set accordingly for building the driver.
$ cd mxm_wifiex/wlan_src/ $ export ARCH=<target architecture, e.g. arm64> $ export CROSS_COMPILE=<cross-toolchain prefix> $ export KERNELDIR=<path to kernel build dir> $ make build
The build results will be stored in the directory ../bin_wlan/: · Driver kernel modules: mlan.ko, moal.ko · Configuration tool: mlanutl (see README_MLAN for usage details)
5.4.3 Downloading the firmware
$ git clone https://github.com/NXP/imx-firmware.git $ cd imx-firmware/nxp/ $ git checkout lf-5.15.5_1.0.0
The Wi-Fi/Bluetooth combo firmware image for the MAYA-W1 series is located at imxfirmware/nxp/FwImage_IW416_SD/sdiouartiw416_combo_v0.bin.
5.4.4 Deployment to the target file system
Copy the compiled driver kernel modules mlan.ko and moal.ko below /lib/modules/<kernelversion> on the target system, for example:
mxm_wifiex/bin_wlan/mlan.ko /lib/modules/<kernel-version>/extra/mlan.ko mxm_wifiex/bin_wlan/moal.ko /lib/modules/<kernel-version>/extra/moal.ko
Then run depmod on the target system to create the module dependencies. Copy the firmware image and driver configuration file to /lib/firmware/nxp/ on the target system:
imx-firmware/nxp/FwImage_IW416_SD/sdiouartiw416_combo_v0.bin /lib/firmware/nxp/sdiouartiw416_combo_v0.bin
imx-firmware/nxp/wifi_mod_para.conf /lib/firmware/nxp/wifi_mod_para.conf
Copy the mlanutl tool to a location on the target file system, for example:
mxm_wifiex/bin_wlan/mlanutl /usr/share/nxp_wireless/mlanutl
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5.4.5 Bluetooth driver
The standard hci_uart driver from the Linux kernel is used for the Bluetooth HCI UART interface. Make sure to enable CONFIG_BT_HCIUART and CONFIG_BT_HCIUART_H4 in the kernel configuration.
5.4.6 Driver loading
Prior to loading the drivers, make sure that the MAYA-W1 series module is detected by the host system on the SDIO bus and reported in the kernel log as shown in the example below:
mmc1: new ultra high speed DDR50 SDIO card at address 0001
The Wi-Fi driver parameters are configured in the /lib/firmware/nxp/wifi_mod_para.conf file in a chipset specific block for MAYA-W1:
SD8978 = { cfg80211_wext=0xf max_vir_bss=1 cal_data_cfg=none ps_mode=1 auto_ds=1 host_mlme=1 fw_name=nxp/sdiouartiw416_combo_v0.bin
}
The Wi-Fi driver and firmware are loaded with the following command:
$ modprobe moal mod_para=nxp/wifi_mod_para.conf
The serial device for the HCI UART interface is attached to the Linux BlueZ stack with the following commands (example using /dev/ttyUSB0):
$ modprobe hci_uart $ hciattach /dev/ttyUSB0 any 3000000 flow $ hciconfig hci0 up
5.4.7 Verification
The version of the loaded Wi-Fi driver and firmware can be verified using the following command:
$ /usr/share/nxp_wireless/mlanutl mlan0 version Version string received: SDIW416---16.92.21.p11.2-MM5X16299.p1-GPL-(FP92)
Use command iw dev to display the available Wi-Fi interfaces (excerpt):
phy#0
Interface wfd0 addr 6e:1d:eb:90:b8:c5 type managed
Interface uap0 addr 6c:1d:eb:90:b9:c5 type AP
Interface mlan0 addr 6c:1d:eb:90:b8:c5 type managed
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Table 24 describes the functions of the Wi-Fi interfaces.
Interface Function
mlan0 Network interface used for station mode functionality. Typically used with wpa_supplicant.
uap0
Network interface used for access-point functionality. Typically used with hostapd.
wfd0
Network interface used for P2P functionality. Can operate in both group owner (GO) and group client (GC) modes.
Table 24: Available Wi-Fi network interfaces
The system/udev managers in modern Linux distributions automatically try to assign
predictable, stable network interface names for all local Ethernet and Wi-Fi interfaces. This
can result in different names being used for the network interfaces. Use the kernel command line option net.ifnames=0 to override this behavior and use the driver default names.
The hciconfig command from BlueZ can be used to verify that the Bluetooth HCI interface is up:
hci0:
Type: Primary Bus: UART BD Address: 6C:1D:EB:90:B8:C4 ACL MTU: 1021:7 UP RUNNING RX bytes:1498 acl:0 sco:0 events:90 errors:0 TX bytes:1270 acl:0 sco:0 commands:90 errors:0
SCO MTU: 120:6
5.5 Usage examples
The Wi-Fi and Bluetooth features and configurations for NXP-based wireless modules on i.MX Linux host platforms are described in the NXP User Manual UM11490 [14]. The document covers the initialization and configuration of the Wi-Fi and Bluetooth interfaces. It is applicable for MAYA-W1 series on i.MX 8 family NXP host processors and other NXP-based wireless modules.
The Wi-Fi features demonstrated in the NXP User Manual [14] are configured with the open source wpa_supplicant/hostapd and Linux utilities. Wi-Fi features include scanning for nearby access points, connecting to an access point, configuring the device as an access point, Wi-Fi security, Wi-Fi Direct, and throughput testing using the iperf utility.
The Bluetooth features use the Linux BlueZ host stack and comprise scan, pair, Bluetooth or Bluetooth Low Energy (LE) device connection, A2DP profile, hands-free profile, and Bluetooth LE device GATT server operation. Guidelines for enabling driver debug logging are also provided.
The manual also explains how to perform radio testing for Wi-Fi and Bluetooth using the open-source drivers.
5.6 Configuration of TX power limits and energy detection
5.6.1 Wi-Fi power table
The Wi-Fi TX power table defines the transmit power levels for the Wi-Fi radio. The power levels are based on regulatory compliance, IEEE 802.11 requirements, and product design constraints. The TX power table can be adjusted to achieve the highest transmit power level for each Wi-Fi channel, bandwidth, and modulation within the constraints defined by the certification.
The correct TX power limits must be applied to the module after startup of the host system and
adjusted after some change of the regulatory domain or country specific requirements during runtime.
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The Wi-Fi TX power levels are configured with the txpwrlimit_2g_cfg_set and txpwrlimit_5g_cfg_set data structures defined in the txpwrlimit_cfg.conf configuration file. The configuration file allows integrators to fine tune specific transmit power levels for the Wi-Fi radio, including:
· Band (2.4, 5 GHz) · Channel · Modulation rate (CCK, OFDM, HT20, HT40) · Channel bandwidth (20, 40 MHz)
Transmit power limit configuration files are provided by u-blox for the certified regulatory domains
accommodated in the available reference designs and Pre-approved antennas. The configuration files for completed certifications are included in the Yocto meta layer.
An example of the txpwrlimit_2g_cfg_set structure for the 2.4 GHz band channels is shown below:
## 2G Tx power limit CFG txpwrlimit_2g_cfg_set={
CmdCode=0x00fb Action:2=1 RSVD:2=0
# do NOT change this line # 1 - SET # do NOT change this line
ChanTRPC.TlvType:2=0x0189 ChanTRPC.TlvLength:2={
TLVStartFreq:2=2407 TLVChanWidth:1=20 TLVChanNum:1=1 TLVPwr:20='0,12,1,11,2,11,3,11,4,11,5,11,6,11,7,0,8,0,9,0' } ChanTRPC.TlvType:2=0x0189 ChanTRPC.TlvLength:2={ TLVStartFreq:2=2407 TLVChanWidth:1=20 TLVChanNum:1=2 TLVPwr:20='0,12,1,16,2,16,3,16,4,16,5,16,6,16,7,0,8,0,9,0' } ChanTRPC.TlvType:2=0x0189 ChanTRPC.TlvLength:2={ TLVStartFreq:2=2407 TLVChanWidth:1=20 TLVChanNum:1=3 TLVPwr:20='0,12,1,16,2,16,3,16,4,16,5,16,6,16,7,15,8,15,9,15' } ... }
The parameters inside txpwrlimit_cfg.conf are described in Table 25.
Parameter
Description
TLVType
Internal parameter set to 0x189. Do not change this value.
TLVStartFreq
Starting frequency of the band for this channel · 2407, 2414 or 2400 for 2.4 GHz · 5000 for 5 GHz
TLVChanWidth Channel bandwidth in MHz (20)
TLVChanNum
Logical 5 MHz channel number (1-255). Channel of the center frequency for HT40 operation in the 2.4 GHz band and primary channel for 40/80 MHz operation in 5 GHz.
TLVPwr:<Length>
Specifies the transmit power limits for specific modulations as a list with the length: <length> of (ModulationGroup,Power) tupels, where ModulationGroup specifies the mapping for the modulation. See also Table 26. Power specifies the Tx power limit in dBm.
Table 25: Parameters in txpwrlimit_cfg.conf file
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The mapping of multiple wireless data rates into ModulationGroup values is shown in Table 26.
ModulationGroup 0 1 2 3 4 5 6 7 8 9
Mode 802.11b 802.11g
802.11n
Bandwidth [MHz] 20 20
20
40
Description CCK (1,2,5.5,11 Mbps) OFDM (6,9,12,18 Mbps) OFDM (24,36 Mbps) OFDM (48,54 Mbps) HT20 (MCS 0,1,2) HT20 (MCS 3,4) HT20 (MCS 5,6,7) HT40 (MCS 0,1,2) HT40 (MCS 3,4) HT40 (MCS 5,6,7)
Table 26: ModulationGroup information
The configuration file example above sets the following transmit power limits for channels 1-3 in the 2.4 GHz band:
· 12 dBm for 802.11b rates on channels 1-3 · 11 dBm for 802.11g and 802.11n HT20 rates on channel 1 · 16 dBm for 802.11g and 802.11n HT20 rates on channels 2 and 3 · 15 dBm for 802.11n HT40 rates on channel 3 (first valid 40 MHz channel)
For HT40 operation in the 2.4 GHz band, the transmit power limits are selected from the
channel of the center frequency. For example, the first 40 MHz channel at the center frequency
2422 MHz (20 MHz channels 1+5) uses the transmit power limits from HT40 values in the
entry with TLVChanNum=3.
An example of the txpwrlimit_5g_cfg_set structure for the 5 GHz channels is shown below:
## 5G Tx power limit CFG txpwrlimit_5g_cfg_set={
CmdCode=0x00fb Action:2=1 RSVD:2=0
# do NOT change this line # 1 - SET # do NOT change this line
ChanTRPC.TlvType:2=0x0189 ChanTRPC.TlvLength:2={
TLVStartFreq:2=5000 TLVChanWidth:1=20 TLVChanNum:1=36 TLVPwr:30='1,15,2,15,3,15,4,15,5,15,6,15,7,15,8,15,9,15' } ChanTRPC.TlvType:2=0x0189 ChanTRPC.TlvLength:2={ TLVStartFreq:2=5000 TLVChanWidth:1=20 TLVChanNum:1=40 TLVPwr:30='1,15,2,15,3,15,4,15,5,15,6,15,7,15,8,15,9,1' } ... }
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The transmit power limit configurations for 40 MHz operation in the 5 GHz band must be
specified for all related 20 MHz channels. For example, the 40 MHz channel at the center frequency 5190 MHz (20 MHz channels 36+40) uses the transmit power limits from HT40 values in the entry with TLVChanNum=36 (secondary channel above primary channel) or TLVChanNum=40 (secondary channel below primary channel), which should be equal.
For the exact power limits used in the u-blox reference design for the various certifications, see the Appendix: Wi-Fi Tx output power limits.
5.6.1.1 Applying the TX power limit configuration
The TX power configuration file txpwrlimit_cfg.conf must first be converted to a binary format before the Wi-Fi driver can use it. The following example command uses the mlanutl tool to create the binary file txpower_US.bin from the configuration file:
mlanutl mlan0 hostcmd txpwrlimit_cfg.conf generate_raw txpower_US.bin
To apply the TX power limit configuration when the driver is loaded, copy the binary file to the firmware directory and add the txpwrlimit_cfg parameter to the wifi_mod_para.conf driver parameter configuration file:
SD8978 = { ... fw_name=nxp/sdiouartiw416_combo_v0.bin txpwrlimit_cfg=nxp/txpower_US.bin
}
The Wi-Fi driver can also be configured with the driver option cntry_txpwr=1 to automatically load the corresponding binary TX power configuration file whenever the regulatory domain is changed. For this, the file name of the TX power files should be txpower_XX.bin, where "XX" is the ISO/IEC 3166 alpha2 country code. The files are expected to reside in the same folder as the firmware.
5.6.1.2 Reading the TX power limit configuration
The current TX power limit configuration can be read from the firmware using the mlanutl tool as shown below:
mlanutl mlan0 get_txpwrlimit <n> [raw_data_file]
where <n>
0:
Get 2.4G txpwrlimit table
0x10: Get 5G sub0 txpwrlimit table
0x11: Get 5G sub1 txpwrlimit table
0x12 Get 5G sub2 txpwrlimit table
0x1f Get all 5G txpwrlimit table
0xff Get both 2G and 5G txpwrlimit table
<raw_data_file> driver will save fw raw data to this file.
5.6.2 Bluetooth TX power levels
The vendor specific HCI command HCI_CMD_UPDATE_TX_MAX_PWR_LVL can be used to update the maximum transmit power level for Bluetooth BR/EDR, as shown in the following usage example:
# hcitool -i hci0 cmd 0x3F 0xEE 0x01 <signed TX power value in dBm> # set max. TX power level to 10 dBm: hcitool -i hci0 cmd 0x3F 0xEE 0x01 0x0A hciconfig hci0 reset
HCI reset is required after this command for the TX power change to take effect. A maximum
TX power level of 12 dBm can be configured.
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Bluetooth LE transmit power level can be set using the vendor specific HCI command HCI_CMD_BLE_WRITE_TRANSMIT_POWER_LEVEL, as shown in the following example:
# hcitool -i hci0 cmd 0x3F 0x87 <signed TX power value in dBm> # set BLE TX power level to 10 dBm: hcitool -i hci0 cmd 0x3F 0x87 0x0A
Bluetooth LE TX power setting will be cleared with HCI reset. A maximum of TX power level of
10 dBm can be configured.
5.6.3 Adaptivity configuration (energy detection)
MAYA-W1 modules support the adaptivity requirements (energy detection) from EN 300 328 and EN 301 893 for Wi-Fi. The Energy Detect mechanism must be explicitly enabled after the startup of the module, and correct detection threshold values must be configured. These threshold values depend on the combined gain of the antenna and antenna trace used in the end-product.
Energy detection is enabled and threshold values are configured through a configuration file, as shown below:
## Set Energy Detect Threshold for EU Adaptivity test
ed_mac_ctrl_v2={
CmdCode=0x0130
# Command code, DO NOT change this line
ed_ctrl_2g.enable:2=0x1
# 0 - disable EU adaptivity for 2.4GHz band
# 1 - enable EU adaptivity for 2.4GHz band
ed_ctrl_2g.offset:2=0x6
# Default Energy Detect threshold
# offset value range: 0x80 to 0x7F
ed_ctrl_5g.enable:2=0x1
# 0 - disable EU adaptivity for 5GHz band
# 1 - enable EU adaptivity for 5GHz band
ed_ctrl_5g.offset:2=0x6
# Default Energy Detect threshold
# offset value range: 0x80 to 0x7F
ed_ctrl_txq_lock:4=0xFF
# DO NOT Change this line
}
The offset values ed_ctrl_2g.offset and ed_ctrl_5g.offset are used to adjust the energy detection thresholds during the EU adaptivity test. Increasing the values results in a more sensitive behavior to compensate for additional attenuation in the antenna path. Decreasing the values lowers the sensitivity.
The following command enables energy detection and configures the detection thresholds according to the settings in the ed_mac_ctrl_V2.conf configuration file:
mlanutl mlan0 hostcmd ed_mac_ctrl_V2.conf ed_mac_ctrl_v2
5.7 Assigning MAC addresses
MAYA-W1 series has four unique MAC addresses reserved for each module. The first MAC address is used for Bluetooth and the second address is used for the Wi-Fi radio. The third and fourth MAC addresses are reserved for use with other local interfaces.
Example 6C:1D:EB:00:4B:40 Bluetooth interface (hci0) 6C:1D:EB:00:4B:41 Wi-Fi station interface (mlan0) 6C:1D:EB:00:4B:42 Reserved for use with other interfaces 6C:1D:EB:00:4B:43 Reserved for use with other interfaces
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The Wi-Fi driver automatically assigns locally unique MAC addresses to any additional Wi-Fi
network interfaces, which are derived from the radio's primary Wi-Fi station interface MAC address. The use of reserved unique MAC addresses is recommended to avoid possible collisions with the MAC addresses of other modules.
The MAC addresses of the interfaces can be configured through an init_cfg.conf file while loading the driver using the driver option init_cfg=nxp/init_cfg.conf. Note that the driver expects the configuration file to be present in a directory relative to /lib/firmware/.
In the following example, the MAC address of the uap0 Wi-Fi interface has been changed to use one of the reserved MAC addresses:
# File: /lib/firmware/nxp/init_cfg.conf # MAC address (interface: address) mac_addr=uap0: 6C:1D:EB:00:4B:42
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6 Handling and soldering
MAYA-W1 series modules are Electrostatic Sensitive Devices that demand the observance of
special handling precautions against static damage. Failure to observe these precautions can result in severe damage to the product.
6.1 ESD handling precautions
As the risk of electrostatic discharge in the RF transceivers and patch antennas of the module is of particular concern, standard ESD safety practices are prerequisite. See also Figure 15.
Consider also:
· When connecting test equipment or any other electronics to the module (as a standalone or PCBmounted device), the first point of contact must always be to local GND.
· Before mounting an antenna patch, connect the device to ground. · When handling the RF pin, do not touch any charged capacitors. Be especially careful when
handling materials like patch antennas (~10 pF), coaxial cables (~50-80 pF/m), soldering irons, or any other materials that can develop charges. · To prevent electrostatic discharge through the RF input, do not touch any exposed antenna area. If there is any risk of the exposed antenna being touched in an unprotected ESD work area, be sure to implement proper ESD protection measures in the design. · When soldering RF connectors and patch antennas to the RF pin on the receiver, be sure to use an ESD-safe soldering iron (tip).
Figure 15: Standard workstation setup for safe handling of ESD-sensitive devices
6.2 Packaging, shipping, storage, and moisture preconditioning
For information pertaining to reels, tapes, or trays, moisture sensitivity levels (MSL), storage, shipment, and drying preconditioning, see the MAYA-W1 series data sheet [1] and Packaging information reference guide [2].
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6.3 Reflow soldering process
MAYA-160 is approved for one-time processes only. MAYA-161 and MAYA-166 are
approved for two-time reflow processes.
MAYA-W1 modules are surface mounted devices supplied on a multi-layer FR4-type PCB with goldplated connection pads. The modules are produced in a lead-free process using lead-free soldering paste. The thickness of solder resist between the host PCB top side and the bottom side of the MAYA-W1 module must be considered for the soldering process.
MAYA-W1modules are compatible with industrial reflow profile for RoHS solders, and "no-clean" soldering paste is strongly recommended.
The reflow profile used is dependent on the thermal mass of the entire populated PCB, the heat transfer efficiency of the oven, and the type of solder paste that is used. The optimal soldering profile must be trimmed for the specific process and PCB layout
The target values shown in Table 27 and Figure 16 are given as general guidelines for a Pb-free
process only. For further information, see also the JEDEC J-STD-020E [7] standard.
Process parameter Pre-heat
Peak
Cooling General
Ramp up rate to TSMIN TSMIN TSMAX tS (from 25°C) tS (Pre-heat) TL tL (time above TL) TP tP (time above TP -5°C) Ramp-down from TL (max) Tto peak Allowed reflow soldering cycles
Unit K/s °C °C s s °C s °C s K/s s -
Table 27: Recommended reflow profile
Target 3 150 200 150 110 217 90 245-250 30 6 300 1 (MAYA-W160) 2 (MAYA-W161 and MAYA-W166 only)
Figure 16: Reflow profile
The lower value of TP and slower ramp down rate is preferred.
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6.3.1 Cleaning
Cleaning the modules is not recommended. Residues underneath the modules cannot be easily removed with a washing process.
· Cleaning with water will lead to capillary effects where water is absorbed in the gap between the baseboard and the module. The combination of residues of soldering flux and encapsulated water leads to short circuits or resistor-like interconnections between neighboring pins. Water will also damage the sticker and the ink-jet printed text.
· Cleaning with alcohol or other organic solvents can result in soldering flux residues flooding into the housing, areas that are not accessible for post-wash inspections. The solvent will also damage the label and the ink-jet printed text.
· Ultrasonic cleaning will permanently damage the module and the crystal oscillators in particular.
For best results use a "no clean" soldering paste and circumvent the need for a cleaning stage after the soldering process.
6.3.2 Other notes
· Boards with combined through-hole technology (THT) components and surface-mount technology (SMT) devices may require wave soldering to solder the THT components. Only a single wave-soldering process is allowed for boards populated with the modules. Miniature Wave Selective Solder processes are preferred over traditional wave soldering processes.
· Hand-soldering is not recommended. · Rework is not recommended. · Conformal coating can affect the performance of the module, which means that it is important to
prevent the liquid from flowing into the module. The RF shields do not provide protection for the module from coating liquids with low viscosity; therefore, care is required while applying the coating. Conformal coating of the module will void the warranty. · Grounding metal covers: Attempts to improve grounding by soldering ground cables, wick, or other forms of metal strips directly onto the EMI covers is done so at the customer's own risk and will void the module warranty. The numerous ground pins on the module are adequate to provide optimal immunity to interferences. · The modules contain components which are sensitive to Ultrasonic Waves. Use of any Ultrasonic Processes (cleaning, welding, etc.) may damage the module. The use of ultrasonic processes during the integration of the module into an end product will void the warranty.
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7 Regulatory compliance
7.1 General requirements
MAYA-W1 series modules are designed to comply with the regulatory demands of Federal Communications Commission (FCC), Innovation, Science and Economic Development Canada (ISED)10 and the CE mark11. This chapter contains instructions on the process needed for an integrator when including the MAYA-W1 module into an end-product.
· Any deviation from the process described may cause the MAYA-W1 series module not to comply with the regulatory authorizations of the module and thus void the user's authority to operate the equipment.
· Any changes to hardware, hosts or co-location configuration may require new radiated emission and SAR evaluation and/or testing.
· The regulatory compliance of MAYA-W1 does not exempt the end-product from being evaluated against applicable regulatory demands; for example, FCC Part 15B criteria for unintentional radiators [9].
· The end-product manufacturer must follow all the engineering and operating guidelines as specified by the grantee (u-blox).
· The MAYA-W1 is for OEM integrators only. · Only authorized antenna(s) may be used. Refer to MAYA-W1 data sheet [1] for the list of
authorized antennas. In the end-product, the MAYA-W1 module must be installed in such a way that only authorized antennas can be used. · The end-product must use the specified antenna trace reference design, as described in the Antenna integration application note [11]. · Any notification to the end user about how to install or remove the integrated radio module is NOT allowed.
If these conditions cannot be met or any of the operating instructions are violated, the u-blox
regulatory authorization will be considered invalid. Under these circumstances, the integrator is responsible to re-evaluate the end-product including the MAYA-W1 series module and obtain their own regulatory authorization, or u-blox may be able to support updates of the u-blox regulatory authorization. See also Antenna requirements.
7.2 FCC/ISED End-product regulatory compliance
u-blox represents that the modular transmitter fulfills the FCC/ISED regulations when operating in authorized modes on any host product given that the integrator follows the instructions as described in this document. Accordingly, the host product manufacturer acknowledges that all host products referring to the FCC ID or ISED certification number of the modular transmitter and placed on the market by the host product manufacturer need to fulfil all of the requirements mentioned below. Noncompliance with these requirements may result in revocation of the FCC approval and removal of the host products from the market. These requirements correspond to questions featured in the FCC guidance for software security requirements for U-NII devices, FCC OET KDB 594280 D02 [16].
The modular transmitter approval of MAYA-W1, or any other radio module, does not exempt the
end product from being evaluated against applicable regulatory demands.
10 Formerly known as IC (Industry Canada). 11 All approvals are still pending
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The evaluation of the end product shall be performed with the MAYA-W1 module installed and operating in a way that reflects the intended end product use case. The upper frequency measurement range of the end product evaluation is the 10th harmonic of 5.8 GHz as described in KDB 996369 D04.
The following requirements apply to all products that integrate a radio module:
· Subpart B - UNINTENTIONAL RADIATORS To verify that the composite device of host and module comply with the requirements of FCC part 15B, the integrator shall perform sufficient measurements using ANSI 63.4-2014.
· Subpart C - INTENTIONAL RADIATORS It is required that the integrator carries out sufficient verification measurements using ANSI 63.10-2013 to validate that the fundamental and out of band emissions of the transmitter part of the composite device complies with the requirements of FCC part 15C.
When the items listed above are fulfilled, the end product manufacturer can use the authorization procedures as mentioned in Table 1 of 47 CFR Part 15.101, before marketing the end product. This means the customer has to either market the end product under a Suppliers Declaration of Conformity (SDoC) or to certify the product using an accredited test lab.
The description is a subset of the information found in applicable publications of FCC Office of Engineering and Technology (OET) Knowledge Database (KDB). We recommend the integrator to read the complete document of the referenced OET KDB's.
· KDB 178919 D01 Permissive Change Policy · KDB 447498 D01 General RF Exposure Guidance · KDB 594280 D01 Configuration Control · KDB 594280 D02 U-NII Device Security · KDB 784748 D01 Labelling Part 15 18 Guidelines · KDB 996369 D01 Module certification Guide · KDB 996369 D02 Module Q&A · KDB 996369 D04 Module Integration Guide
7.2.1 Referring to the u-blox FCC/ISED certification ID
If the General requirements, FCC/ISED End-product regulatory compliance and all Antenna requirements are met, the u-blox modular FCC/ISED regulatory authorization is valid and the endproduct may refer to the u-blox FCC ID and ISED certification number. u-blox may be able to support updates to the u-blox regulatory authorization by adding new antennas to the u-blox authorization for example. See also Antenna requirements.
To use the u-blox FCC / ISED grant and refer to the u-blox FCC ID / ISED certification ID, the
integrator must confirm with u-blox that all requirements associated with the Configuration control and software security of end-products are fulfilled.
7.2.2 Obtaining own FCC/ISED certification ID
Integrators who do not want to refer to the u-blox FCC/ISED certification ID, or who do not fulfil all requirements to do so may instead obtain their own certification. With their own certification, the integrator has full control of the grant to make changes.
Integrators who want to base their own certification on the u-blox certification can do so via a process called "Change in ID" (FCC) / "Multiple listing" (ISED). With this, the integrator becomes the grantee of a copy of the u-blox FCC/ISED certification. u-blox will support with an approval letter that shall be filed as a Cover Letter exhibit with the application.
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For modules where the FCC ID / ISED certification ID is printed on the label, the integrator must
replace the module label with a new label containing the new FCC/ISED ID. For a description of the labeling requirements, see also the MAYA-W1 series data sheet [1].
It is the responsibility of the integrator to comply with any upcoming regulatory requirements.
7.2.3 Antenna requirements
In addition to the general requirement to use only authorized antennas, the u-blox grant also requires a separation distance of at least 20 cm from the antenna(s) to all persons. The antenna(s) must not be co-located with any other antenna or transmitter (simultaneous transmission) as well. If this cannot be met, a Permissive Change as described below must be made to the grant.
To support verification activities that may be required by certification laboratories, customers
applying for Class-II Permissive changes must implement the setup described in Software.
7.2.3.1 Separation distance
If the required separation distance of 20 cm cannot be fulfilled, a SAR evaluation must be performed. This consists of additional calculations and/or measurements. The result must be added to the grant file as a Class II Permissive Change.
7.2.3.2 Co-location (simultaneous transmission)
If the module is to be co-located with another transmitter, additional measurements for simultaneous transmission are required. The results must be added to the grant file as a Class II Permissive Change.
7.2.3.3 Adding a new antenna for authorization
If the authorized antennas and/or antenna trace design cannot be used, the new antenna and/or antenna trace designs must be added to the grant file. This is done by a Class I Permissive Change or a Class II Permissive Change, depending on the specific antenna and antenna trace design.
· Antennas of the same type and with less or same gain as those included in the list of Pre-approved antennas can be added under a Class I Permissive Change.
· Antenna trace designs deviating from the u-blox reference design and new antenna types are added under a Class II Permissive Change.
· For 5 GHz modules, the combined minimum gain of antenna trace and antenna must be greater than 0 dBi to comply with DFS testing requirements.
Integrators intending to refer to the u-blox FCC ID / ISED certification ID must contact their local
support team to discuss the Permissive Change Process. Class II Permissive Changes are subject to NRE costs.
7.2.4 Configuration control and software security of end-products
"Modular transmitter" hereafter refers to MAYA-W160 (FCC ID XPYMAYAW160),
MAYA-W161 (FCC ID XPYMAYAW161), and MAYA-W166 (FCC ID XPYMAYAW166).
As the end-product must comply with the requirements addressed by the OET KDB 594280 [15], the host product integrating the MAYA-W1 must comply with the following requirements:
· Upon request from u-blox, the host product manufacturer will provide all of the necessary information and documentation to demonstrate how the requirements listed below are met.
· The host product manufacturer will not modify the modular transmitter hardware.
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· The configuration of the modular transmitter when installed into the host product must be within the authorization of the modular transmitter at all times and cannot be changed to include unauthorized modes of operation through accessible interfaces of the host product. The Wi-Fi Tx output power limits must be followed. In particular, the modular transmitter installed in the host product will not have the capability to operate on the operating channels/frequencies referred to in the section(s) below, namely one or several of the following channels: 12 (2467 MHz), 13 (2472 MHz), 120 (5600 MHz), 124 (5620 MHz), and 128 (5640 MHz). The channels 12 (2467 MHz), 13 (2472 MHz), 120 (5600 MHz), 124 (5620 MHz), and 128 (5640 MHz) are allowed to be used only for modules that are certified for the usage ("modular transmitter"). Customers must verify that the module in use is certified as supporting DFS client/master functionality.
· The host product uses only authorized firmware images provided by u-blox and/or by the manufacturer of the RF chipset used inside the modular transmitter.
· The configuration of the modular transmitter must always follow the requirements specified in Operating frequencies and cannot be changed to include unauthorized modes of operation through accessible interfaces of the host product.
· The modular transmitter must when installed into the host product have a regional setting that is compliant with authorized US modes and the host product is protected from being modified by third parties to configure unauthorized modes of operation for the modular transmitter, including the country code.
· The host product into which the modular transmitter is installed does not provide any interface for the installer to enter configuration parameters into the end product that exceeds those authorized.
· The host product into which the modular transmitter is installed does not provide any interface to third parties to upload any unauthorized firmware images into the modular transmitter and prevents third parties from making unauthorized changes to all or parts of the modular transmitter device driver software and configuration.
OET KDB 594280 D01 [15] lists the topics that must be addressed to ensure that the end-
product specific host meets the Configuration Control requirements.
OET KDB 594280 D02 [15] lists the topics that must be addressed to ensure that the end-
product specific host meets the Software Security Requirements for U-NII Devices.
7.2.5 Operating frequencies
MAYA-W1 802.11b/g/n operation outside the 24122462 MHz band is prohibited in the US and Canada and 802.11a/n operation in the 56005650 MHz band is prohibited in Canada. Configuration of the module to operate on channels 1213 and 120128 must be prevented accordingly. The channels allowed while operating under the definition of a master or client device12 are described in Table 28.
12 47 CFR §15.202
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Channel number 1 11 12 13
Channel center frequency [MHz] 2412 2462 2467 2472
36 48
5180 5240
52 64 100 116
5260 5320 5500 5580
120 128
5600 5640
132 144 149 165
5660 5720 5745 5825
Allowed channels Yes No
Yes
Yes13 Yes13
No
Yes13 Yes
Remarks
Canada (ISED): Devices are restricted to indoor operation only and the end product must be labelled accordingly.
USA (FCC): Client device operation allowed under KDB 905462
Table 28: Allowed channel usage under FCC/ISED regulation
15.407 (j) Operator Filing Requirement:
Before deploying an aggregate total of more than one thousand outdoor access points within the 5.155.25 GHz band, parties must submit a letter to the Commission acknowledging that, should harmful interference to licensed services in this band occur, they will be required to take corrective action. Corrective actions may include reducing power, turning off devices, changing frequency bands, and/or further reducing power radiated in the vertical direction. This material shall be submitted to Laboratory Division, Office of Engineering and Technology, Federal Communications Commission, 7435 Oakland Mills Road, Columbia, MD 21046. Attn: U-NII Coordination, or via Web site at https://www.fcc.gov/labhelp with the subject line: "U-NII-1 Filing".
7.2.6 End product labeling requirements
For an end-product using the MAYA-W1, there must be a label containing, at least, the following information:
This device contains FCC ID: (XYZ)(UPN) IC: (CN)-(UPN)
(XYZ) represents the FCC "Grantee Code", this code may consist of Arabic numerals, capital letters, or other characters, the format for this code will be specified by the Commission's Office of Engineering and Technology14. (CN) is the Company Number registered at ISED. (UPN) is the Unique Product Number decided by the grant owner.
The label must be affixed on an exterior surface of the end product such that it will be visible upon inspection in compliance with the modular labeling requirements of OET KDB 784748. The host user manual must also contain clear instructions on how end users can find and/or access the FCC ID of the end product.
The label on the MAYA-W1 module containing the original FCC ID acquired by u-blox can be replaced with a new label stating the end-product's FCC/ISED ID in compliance with the modular labeling requirements of OET KDB 784748.
13 DFS certification is pending. 14 47 CFR 2.926
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FCC end product labeling In accordance with 47 CFR § 15.19, the end product shall bear the following statement in a conspicuous location on the device:
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: This device may not cause harmful interference, and This device must accept any interference received, including interference that may cause undesired operation.
ISED end product labeling The end product shall bear the following statement in both English and French in a conspicuous location on the device:
Operation is subject to the following two conditions: This device may not cause interference, and This device must accept any interference, including interference that may cause undesired operation of the device.
Son utilisation est soumise aux deux conditions suivantes: Cet appareil ne doit pas causer d'interférences et il doit accepter toutes interférences reçues, y compris celles susceptibles d'avoir des effets indésirables sur son fonctionnement.
Labels of end products capable to operate within the band 51505250 MHz shall also include:
For indoor use only
Pour usage intérieur seulement
When the device is so small or for such use that it is not practicable to place the statements above on it, the information shall be placed in a prominent location in the instruction manual or pamphlet supplied to the user or, alternatively, shall be placed on the container in which the device is marketed. However, the FCC/ISED ID label must be displayed on the device as described above. In case, where the final product will be installed in locations where the end-consumer is unable to see the FCC/ISED ID and/or this statement, the FCC/ISED ID and the statement shall also be included in the end-product manual.
7.3 CE End-product regulatory compliance
7.3.1 Safety standard
In order to fulfill the safety standard EN 60950-1 [8], the MAYA-W1 module must be supplied with a Class-2 Limited Power Source.
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7.3.2 CE Equipment classes
In accordance with Article 1 of Commission Decision 2000/299/EC15, MAYA-W1 is defined as either Class-1 or Class-2 radio equipment, the end-product integrating MAYA-W1 inherits the equipment class of the module.
Guidance on end product marking, according to the RED can be found at: http://ec.europa.eu/ The restrictions while operating the MAYA-W1 in Wi-Fi mode in the European countries are
shown in section "European Union regulatory compliance" of the MAYA-W1 data sheet [1].
The EIRP of the MAYA-W1 module must not exceed the limits of the regulatory domain that the
module operates in. Depending on the host platform implementation and antenna gain, integrators must limit the maximum output power of the module through the host software. See Pre-approved antennas for the list of approved antennas and information about the corresponding maximum transmit power levels.
7.4 Pre-approved antennas
This section lists the different external antennas that are pre-approved for use with MAYA-W1 series modules.
7.4.1 Wi-Fi / Bluetooth dual band antennas
For Bluetooth and Wi-Fi operation in the 2.4 GHz band and Wi-Fi operation in the 5 GHz band MAYAW1 has been tested and approved for use with the dual-band antennas shown in Table 29.
Manufacturer Part Number
Antenna type
Linx
ANT-DB1-RAF-RPS Dual-band dipole antenna
Peak gain [dBi] 2.4 GHz band 2.5
Validated regulatory domain 5 GHz band
4.6
FCC/ISED, RED
Table 29: List of approved dual-band antennas
Important: To be compliant to FCC §15.407(a) the EIRP is not allowed to exceed 125 mW
(21 dBm) at any elevation angle above 30° (measured from the horizon) when operated as an outdoor access point in U-NII-1 band, 5.150-5.250 GHz.
7.4.2 Bluetooth antennas
The single band antennas tested and approved for Bluetooth transmission with MAYA-W1 are shown in Table 30.
Manufacturer Part number
Antenna type
Linx
ANT-2.4-CW-RCT-RP Single-band dipole antenna
Peak gain [dBi] 2.4 GHz band 2.2
Validated regulatory domain
FCC/ISED, RED
Table 30: List of approved single-band antennas
15 2000/299/EC: Commission Decision of 6 April 2000 establishing the initial classification of radio equipment and telecommunications terminal equipment and associated identifiers.
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8 Product testing
8.1 u-blox in-line production testing
As part of our focus on high quality products, u-blox maintain stringent quality controls throughout the production process. This means that all units in our manufacturing facilities are fully tested and that any identified defects are carefully analyzed to improve future production quality.
The Automatic test equipment (ATE) deployed in u-blox production lines logs all production and measurement data from which a detailed test report for each unit can be generated. Figure 17 shows the ATE typically used during u-blox production.
u-blox in-line production testing includes:
· Digital self-tests (firmware download, MAC address programming) · Measurement of voltages and currents · Functional tests (host interface communication) · Digital I/O tests · Measurement and calibration of RF characteristics in all supported bands, including RSSI
calibration, frequency tuning of reference clock, calibration of transmitter power levels, etc. · Verification of Wi-Fi and Bluetooth RF characteristics after calibration, like modulation accuracy,
power levels, and spectrum, are checked to ensure that all characteristics are within tolerance when the calibration parameters are applied.
Figure 17: Automatic test equipment for module test
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8.2 OEM manufacturer production test
As all u-blox products undergo thorough in-series production testing prior to delivery, OEM manufacturers do not need to repeat any firmware tests or measurements that might otherwise be necessary to confirm RF performance. Testing over analog and digital interfaces is also unnecessary during an OEM production test.
OEM manufacturer testing should ideally focus on:
· Module assembly on the device; it should be verified that: o Soldering and handling process did not damage the module components o All module pins are well soldered on the application board o There are no short circuits between pins
· Component assembly on the device; it should be verified that: o Communication with host controller can be established o The interfaces between module and device are working o Overall RF performance test of the device including antenna
In addition to this testing, OEMs can also perform other dedicated tests to check the device. For example, the measurement of module current consumption in a specified operating state can identify a short circuit if the test result deviates that from that taken against a "Golden Device".
The standard operational module firmware and test software on the host can be used to perform functional tests (communication with the host controller, check interfaces) and perform basic RF performance testing. Special manufacturing firmware can also be used to perform more advanced RF performance tests.
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Appendix
A Glossary
Abbreviation AEC AP API ATE BT CDM CE CTS DC DDR DFS DHCP EDR EEPROM EIRP EMI ESD ESL ESR FCC GND GPIO HBM HS HCI ISED I2C KDB LAN LDO LED LPO LTE MAC MMC MWS NRE NSMD OEM OET OS
Definition Automotive Electronics Council Access Point Application Programming Interface Automatic Test Equipment Bluetooth Charged Device Model European Conformity Clear to Send Direct Current Double Data Rate Dynamic Frequency Selection Dynamic Host Configuration Interface Enhanced Data Rate Electrically Erasable Programmable Read-Only Memory Equivalent Isotropic Radiated Power Electromagnetic Interference Electro Static Discharge Equivalent Series Inductance Equivalent Series Resistance Federal Communications Commission Ground General Purpose Input/Output Human Body Model High-Speed Host Controller Interface Innovation, Science and Economic Development Canada Inter-Integrated Circuit Knowledge Database Local Area Network Low Drop Out Light-Emitting Diode Low Power Oscillator Long Term Evolution Medium Access Control Multi Media Card Mobile Wireless Standards Non-recurring engineering Non Solder Mask Defined Original equipment manufacturer Office of Engineering and Technology Operating System
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Abbreviation PCB PCI PCIe PCM PHY PMU RF RSDB RST SDIO SMD SMPS SMT SSID STA TBD THT UART VCC VIO VSDB VSWR WFD WLAN WPA
Definition Printed Circuit Board Peripheral Component Interconnect PCI Express Pulse-code modulation Physical layer (of the OSI model) Power Management Unit Radio Frequency Real Simultaneous Dual Band Request to Send Secure Digital Input Output Solder Mask Defined Switching Mode Power Supply Surface-Mount Technology Service Set Identifier Station To be Decided Through-Hole Technology Universal Asynchronous Receiver-Transmitter IC power-supply pin Input offset voltage Virtual Simultaneous Dual Band Voltage Standing Wave Ratio Wi-Fi Direct Wireless local area network Wi-Fi Protected Access
Table 31: Explanation of the abbreviations and terms used
B Wi-Fi transmit output power limits
Pending.
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Related documents
[1] MAYA-W1 series data sheet, UBX-21006380 [2] Packaging information reference, UBX-14001652 [3] u-blox Limited Use License Agreement, LULA-M [4] IEC EN 61000-4-2 - Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement
techniques Electrostatic discharge immunity test [5] ETSI EN 301 489-1 - Electromagnetic compatibility and Radio spectrum Matters (ERM);
ElectroMagnetic Compatibility (EMC) standard for radio equipment and services; Part 1: Common technical requirements [6] IEC61340-5-1 - Protection of electronic devices from electrostatic phenomena General requirements [7] JEDEC J-STD-020E - Moisture/Reflow Sensitivity Classification for Nonhermetic Surface Mount Devices [8] ETSI EN 60950-1:2006 - Information technology equipment Safety Part 1: General requirements [9] FCC Regulatory Information, Title 47 Telecommunication [10] JESD51 Overview of methodology for thermal testing of single semiconductor devices [11] Antenna Integration application note, TBD [12] Embedded Linux for i.MX Applications Processors [13] MCUXpresso Software Development Kit (SDK) [14] NXP UM11490, Feature Configuration Guide for NXP-based Wireless Modules on i.MX 8M Quad EVK [15] FCC guidance 594280 D01 Configuration Control v02 r01, [16] FCC guidance 594280 D02 U-NII Device Security v01r03 [17] MAYA-W1 product summary, UBX-20047825
For product change notifications and regular updates of u-blox documentation, register on our
website, www.u-blox.com.
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Revision history
Revision R01 R02
Date 21-Jul-2021 04-Jan-2022
Name lber, mzes lber, mzes, mape
R03 R04
04-Mar-2022 lber 04-May-2022 lber
R05
04-Jul-2022
lber, mzes
Contact
Comments
Initial release.
Editorial changes, including content restructuring in several sections throughout the document. SDIO line Pull-up resistor recommendation added in SDIO 3.0 interface and SDIO 3.0. Aligned Pin list with the MAYA-W1 data sheet. Revised Module integration.
Updated Block diagrams in Figure 1 and Figure 2 (removed LDO with 1V8 output supply shown in previous document release). Alternative start-up sequence added to Figure 7 in Power-up sequence section.
Affirmed MAYA-W166-00B as the product variant with integrated antenna and included details of its integration in Antenna interfaces. Extended document scope to include product variant MAYA-W16601B in Document information. Reorganized power management information under new Power states section and created new System function interfaces section.
Added Pre-approved antennas. Updated Software architecture and added Linux drivers bring-up, Configuration of TX power limits and energy detection, and Assigning MAC addresses in the Software section. Updated Configuration control and software security of endproducts. Updated contact information.
For further support and contact information, visit us at www.u-blox.com/support.
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References
Home | u-blox- Home | u-blox
- Contact u-blox | u-blox
List of IEC standards - Wikipedia
GitHub - nxp-imx/imx-firmware- GitHub - nxp-imx/imx-firmware
OET Knowledge Database (KDB)
MCUXpresso SDK | Software Development for Kinetis, LPC, and i.MX MCUs | NXP Semiconductors- Embedded Linux for i.MX Applications Processors | NXP Semiconductors
- u-blox.com/docs/UBX-20047825
Related FCC IDs:
- XPYMAYAW161 - u-blox AG WLAN/Bluetooth host-based multiradio module MAYA W161 [MAYAW161]
- XPYMAYAW166 - u-blox AG WLAN/Bluetooth host-based multiradio module MAYA W166 [MAYAW166] Microsoft Word for Microsoft 365