PICMG COM-HPC Carrier Design Guide

Rev. 2.1

Christian Eder, congatec, Stefan Milnor, Kontron

Carrier Design Guide

COM-HPC - PICMG

PICMG COM-HPC Carrier Design Guide

COM-HPC Carrier Design Guide

COM-HPC Computer-on-Module - congatec | Mouser

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Document Document DEVICE REPORTPICMG COM-HPC CDG R2 1

COM-HPC® Carrier Design Guide
Guidelines for Designing COM-HPC® Carrier Boards
August 10, 2023
Rev. 2.1
This Design Guide is not a specification. It provides COM-HPC® Carrier implementation information but does not replace the PICMG COM-HPC® specification. The full COM-HPC® specification is needed in conjunction with this Design Guide for signal descriptions, signal integrity information and loss budgets, Module and Carrier connector pin-outs, PCB mechanical details and more.

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© Copyright 2021, 2022, 2023 PCI Industrial Computer Manufacturers Group. The attention of adopters is directed to the possibility that compliance with or adoption of PICMG® specifications may require use of an invention covered by patent rights. PICMG® shall not be responsible for identifying patents for which a license may be required by any PICMG® specification or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. PICMG® specifications are prospective and advisory only. Prospective users are responsible for protecting themselves against liability for infringement of patents.
NOTICE: The information contained in this document is subject to change without notice. The material in this document details a PICMG® specification in accordance with the license and notices set forth on this page. This document does not represent a commitment to implement any portion of this specification in any company's products.
WHILE THE INFORMATION IN THIS PUBLICATION IS BELIEVED TO BE ACCURATE, PICMG® MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, ANY WARRANTY OF TITLE OR OWNERSHIP, IMPLIED WARRANTY OF MERCHANTABILITY OR WARRANTY OF FITNESS FOR PARTICULAR PURPOSE OR USE.
In no event shall PICMG® be liable for errors contained herein or for indirect, incidental, special, consequential, reliance or cover damages, including loss of profits, revenue, data or use, incurred by any user or any third party. Compliance with this specification does not absolve manufacturers of equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.).
IMPORTANT NOTICE: This document includes references to specifications, standards or other material not created by PICMG. Such referenced materials will typically have been created by organizations that operate under IPR policies with terms that vary widely, and under process controls with varying degrees of strictness and efficacy. PICMG has not made any enquiry into the nature or effectiveness of any such policies, processes or controls, and therefore ANY USE OF REFERENCED MATERIALS IS ENTIRELY AT THE RISK OF THE USER. Users should therefore make such investigations regarding referenced materials, and the organizations that have created them, as they deem appropriate.
PICMG®, COM-HPC®, CompactPCI®, AdvancedTCA®, ATCA®, AdvancedMC®, CompactPCI® Express, COMHPC®, MicroTCA®, SHB Express®, and the PICMG, CompactPCI, AdvancedTCA, µTCA and ATCA logos are registered trademarks, and cPCI Serial SpaceTM, xTCATM, IRTMTM and the IRTM logo are trademarks of the PCI Industrial Computer Manufacturers Group. All other brand or product names may be trademarks or registered trademarks of their respective holders.

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Table of Contents
1. Preface.................................................................................................................................... 9 1.1. About This Document.......................................................................................................................9 1.2. Intended Audience.............................................................................................................................9 1.3. No Special Word Usage....................................................................................................................9 1.4. No Statements of Compliance..........................................................................................................9 1.5. Correctness Disclaimer.....................................................................................................................9 1.6. Name and Logo Usage......................................................................................................................9 1.7. Intellectual Property........................................................................................................................11
1.7.1. Necessary IPR Claims (Referring to Mandatory or Recommended Features).......................................11 1.7.2. Unnecessary Claims (Referring to Optional Features or Non-normative Elements)..............................11 1.7.3. Third Party Disclosures...........................................................................................................................12 1.7.4. Copyright Notice......................................................................................................................................12 1.7.5. Trademarks.............................................................................................................................................12 1.8. Acronyms, Abbreviations and Definitions Used..........................................................................13 1.9. Applicable Documents and Standards..........................................................................................16
2. COM-HPC Interfaces............................................................................................................18 2.1. COM-HPC Client and Server Pinout Differences..........................................................................18
3. Reference Schematics and Block Diagrams.....................................................................22 3.1. Sources for Technical Materials.....................................................................................................22 3.2. Schematic Conventions..................................................................................................................22 3.3. Ethernet NBASE-T...........................................................................................................................23 3.4. Ethernet KR and KR4......................................................................................................................24
3.4.1. Ethernet KR CEI Block Diagrams...........................................................................................................24 3.4.2. PHY Addresses.......................................................................................................................................32 3.5. Serial ATA.........................................................................................................................................33 3.5.1. Cabled SATA...........................................................................................................................................33 3.5.2. mSATA SSDs..........................................................................................................................................34 3.5.3. M.2 SATA SSDs......................................................................................................................................34 3.6. PCI Express......................................................................................................................................35 3.6.1. General Notes.........................................................................................................................................35 3.6.2. PCI Express Coupling Capacitor Locations............................................................................................36 3.6.3. PCIe Group 0 Low Examples: Device Down, mini-PCIe, M.2 E-Key, M.2 B-Key...................................37 3.6.4. Dual PCIe x4 M.2 M Key NVME SSDs Examples on PCIe Group 0 High.............................................42 3.6.5. PCIe x16 Slot Card Site on PCIe Group 1..............................................................................................45 3.6.6. PCIe Group 2..........................................................................................................................................46 3.6.7. MXM-3 Graphics Card Module on Carrier..............................................................................................50 3.6.8. PCIe Reference Clocks...........................................................................................................................51 3.6.9. PCIe Redrivers and Retimers.................................................................................................................56 3.7. USB...................................................................................................................................................57 3.7.1. USB Terms and General Information......................................................................................................57 3.7.2. USB 2.0 Type-A Example........................................................................................................................59 3.7.3. USB 3.2 Gen 1 and Gen 2 Type-A..........................................................................................................60 3.7.4. USB 3 Redrivers.....................................................................................................................................60 3.7.5. USB Type-C Overview............................................................................................................................61

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3.7.6. USB Type-C Port Multiplexers................................................................................................................65 3.7.7. USB Type-C Power Delivery Controllers................................................................................................66 3.7.8. USB Type-C Port Protection Components..............................................................................................67 3.7.9. USB 3.2 Gen 2x1 Type-C Basic Implementation....................................................................................68 3.7.10. USB 3.2 Gen 2x2 Type-C Example Implementation.............................................................................70 3.7.11. USB4.....................................................................................................................................................76 3.8. Boot SPI on Carrier..........................................................................................................................82 3.9. eSPI...................................................................................................................................................86 3.10. DisplayPort Over DDI....................................................................................................................87 3.11. HDMI Over DDI...............................................................................................................................90 3.12. eDP..................................................................................................................................................92 3.12.1. eDP / DP Conversions to Other Video Formats....................................................................................94 3.13. MIPI-CSI Camera Interface............................................................................................................95 3.14. Audio Interfaces.............................................................................................................................96 3.14.1. General Discussion...............................................................................................................................96 3.14.2. MIPI SoundWire Summary...................................................................................................................96 3.14.3. I2S Implementations on COM-HPC......................................................................................................99 3.15. Asynchronous Serial Port Interfaces.........................................................................................100 3.15.1. COM-HPC UART Interfaces...............................................................................................................100 3.15.2. Legacy Compatibility With 16C550 UART Register Set.....................................................................101 3.15.3. Alternative / Additional Carrier Board UART Implementations............................................................102 3.16. I2C / I3C Ports..............................................................................................................................103 3.16.1. I2C Addressing....................................................................................................................................104 3.16.2. I2C0 Example: Carrier I2C Device in S0 Power Domain....................................................................105 3.16.3. I2C Bus Buffers / Level Translators....................................................................................................105 3.16.4. I2C1 (COM-HPC) and Optional I3C Support......................................................................................106 3.17. Port 80h Debug Display Over COM-HPC USB_PD_I2C............................................................107 3.18. Carrier BMC with IPMB Link to Module.....................................................................................108 3.19. General Purpose SPI...................................................................................................................112 3.20. Rapid Shutdown...........................................................................................................................112 3.21. Thermal Protection......................................................................................................................113 3.22. System Management Bus (SMBus)............................................................................................114 3.23. General Purpose Inputs / Outputs.............................................................................................115 3.24. Module Type Detection and Protection......................................................................................116
4. PCB Design Rule Summaries............................................................................................118 4.1. High Speed PCB Design Information ­ Design Guides and Books..........................................118
4.1.1. Intel and AMD Design Guides...............................................................................................................118 4.1.2. Books on High Speed PCB Design Principles......................................................................................119 4.2. High Speed Serial Interfaces ­ General PCB Design Rules......................................................120 4.3. PCB Design Rule Summaries - High Speed Differential Pair Serial Interfaces.......................123 4.3.1. NBASE-T Design Rule Summary.........................................................................................................123 4.3.2. Ethernet KR Design Rule Summary.....................................................................................................124 4.3.3. SATA Design Rule Summary................................................................................................................125 4.3.4. PCIe Design Rule Summary.................................................................................................................126 4.3.5. USB 2.0 Design Rule Summary............................................................................................................127 4.3.6. USB 3.2 and USB4 Design Rule Summaries.......................................................................................128

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4.3.7. DisplayPort Design Rule Summary.......................................................................................................130 4.3.8. eDP Design Rule Summary..................................................................................................................131 4.3.9. HDMI Design Rule Summary................................................................................................................132 4.4. PCB Design Rules for Single Ended (SE) Interfaces.................................................................133
5. Mechanical Considerations.............................................................................................. 134 5.1. Heat Spreader / Module / Carrier Attachment Details................................................................134
5.1.1. Heat Spreader to Module Attachment Notes........................................................................................134 5.1.2. Heat Spreader / Module Assembly Attachment to Carrier and Chassis...............................................135 5.2. Alternative COM-HPC Board Stack Assembly Suggestion.......................................................140 5.2.1. Precision Jack Screw Standoffs............................................................................................................140 5.3. Carrier Board Stiffener..................................................................................................................142
6. Appendices.........................................................................................................................146 6.1. Appendix A: Synchronous Ethernet............................................................................................146 6.2. Appendix B: Alternative eDP Example........................................................................................150 6.3. Appendix C: eSPI Header Example..............................................................................................157 6.4. Appendix D: Useful Books ­ General x86 Computer Topics.....................................................158 6.5. Appendix E: Revision History......................................................................................................159

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Index of Tables
Table 1: Acronyms, Abbreviations and Definitions Used....................................................................................13 Table 2: Client and Server Type Pinout Difference Table...................................................................................18 Table 3: Power Net Naming...............................................................................................................................22 Table 4: MDIO Addresses for Intel POR External PHYs....................................................................................32 Table 5: mSATA Pin Mapping Relative to miniPCIe...........................................................................................34 Table 6: PCIe Maximum Allowable Clock Jitter..................................................................................................51 Table 7: PCIe Clock Buffer Modes.....................................................................................................................52 Table 8: PCIe Clock Buffer Vendors and Part Numbers....................................................................................53 Table 9: PCIe Redrivers and Retimers...............................................................................................................56 Table 10: USB.org Branding Term Summary.....................................................................................................57 Table 11: USB Type-A Pin-Out...........................................................................................................................58 Table 12: USB 3 Redrivers.................................................................................................................................60 Table 13: USB Type-C Connector Pin-out.........................................................................................................62 Table 14: USB Type-C Port Multiplexers ­ Possible Modes..............................................................................65 Table 15: Boot SPI Socket Suggestions............................................................................................................84 Table 16: DisplayPort Redrivers and Retimers..................................................................................................89 Table 17: SoundWire Audio CODECs................................................................................................................97 Table 18: Alternative / Additional Carrier Board UART Implementations.........................................................102 Table 19: I2C Operating Modes.......................................................................................................................103 Table 20: I2C Bus Buffers / Level Translators / Power Domain Isolation.........................................................105 Table 21: COM-HPC Type Definitions..............................................................................................................116 Table 22: Intel and AMD Design Guides..........................................................................................................118 Table 23: General Design Rules for High Speed Serial interfaces..................................................................121 Table 24: NBASE-T Design Rule Summary.....................................................................................................123 Table 25: Ethernet KR Design Rule Summary.................................................................................................124 Table 26: SATA Design Rule Summary............................................................................................................125 Table 27: PCIe Design Rule Summary............................................................................................................126 Table 28: USB 2.0 Design Rule Summary.......................................................................................................127 Table 29: USB 3.2 and USB4 Design Rule Summaries...................................................................................128 Table 30: DisplayPort Design Rule Summary..................................................................................................130 Table 31: HDMI Design Rule Summary...........................................................................................................132 Table 32: Design Rules for Single Ended Interfaces.......................................................................................133 Table 33: SDP Use in Figure Above.................................................................................................................148 Table 34: SyncE / PTP Matrix..........................................................................................................................149 Table 35: General Books on x86 Computer Topics..........................................................................................158 Table 36: Revision History................................................................................................................................159

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Table of Figures
Figure 1: Schematic Conventions......................................................................................................................22 Figure 2: NBASE-T............................................................................................................................................23 Figure 3: Intel SoC with CEI Boundary..............................................................................................................25 Figure 4: Intel CEI 4x SFP28.............................................................................................................................26 Figure 5: Intel CEI 4x SFP28 with Retimer C827/XL827...................................................................................27 Figure 6: Intel CEI QSFP28 with Retimer C827/XL827.....................................................................................28 Figure 7: Intel CEI 4x 10GBASE-T Copper PHY X557-AT4..............................................................................29 Figure 8: Intel CEI 4x 1GBASE-T Copper PHY Marvell 88E1543.....................................................................30 Figure 9: AMD SoC 4xSFP+ with CS4223 Retimer...........................................................................................31 Figure 10: Serial ATA - Cabled...........................................................................................................................33 Figure 11: PCIe Data Line Coupling Capacitor Positions (MXM-3 Cards Excluded).........................................36 Figure 12: PCIe Device Down on Carrier ­ PCIe Group 0 Low ­ PCIe Lane 0.................................................37 Figure 13: Mini-PCIe Site ­ PCIe Group 0 Low ­ PCIe Lane 1.........................................................................38 Figure 14: M.2 E-Key Site ­ WiFi Cards ­ PCIe Group 0 Low ­ PCIe Lane 2..................................................39 Figure 15: M.2 B-Key Site ­ Cell Modem Cards ­ PCIe Group 0 Low ­ PCIe Lane 3......................................40 Figure 16: Clock and Reset Buffers for PCIe Group 0 Low Example Circuits...................................................41 Figure 17: M.2 M-Key Site for NVME SSD Card #1 in Group 0 High PCIe Lanes 8:11....................................42 Figure 18: M.2 M -Key Site for NVME SSD #2 in Group 0 PCIe Lanes 12:15..................................................43 Figure 19: Clock Buffer and Reset for PCIe Dual M.2 NVME SSD PCIe Group 0 High....................................44 Figure 20: PCIe x16 Slot Card Site on PCIe Group 1 PCIe Lanes 16:31..........................................................45 Figure 21: PCIe x8 Slot Card Site on PCIe Group 2 PCIe Lanes 32:39............................................................46 Figure 22: PCIe x4 Slot Card Site on PCIe Group 2 PCIe Lanes 40:43............................................................47 Figure 23: PCIe x4 Slot Card Site on PCIe Group 2 PCIe Lanes 44:47............................................................48 Figure 24: PCIe Clock Buffer and Reset Buffer for PCIe Group 2 Example......................................................49 Figure 26: USB 2.0 Type-A Example.................................................................................................................59 Figure 27: USB Type-C Receptacle and Plug Images.......................................................................................62 Figure 28: USB Type-C Receptacle Pin-Out ­ Looking Into Carrier Receptacle...............................................62 Figure 29: USB Type-C Basic Implementation: USB 3.2 Gen 1 and Gen 2......................................................69 Figure 30: USB 3.2 Gen 2x2 Type-C (1 of 6): Option Resistors for Type-C or Type-A......................................70 Figure 31: USB 3.2 Gen 2x2 Type-C (2 of 6): Port Multiplexer and Redriver....................................................71 Figure 32: USB 3.2 Gen 2x2 Type-C (3 of 6): EMI Mitigation and ESD Protection...........................................72 Figure 33: USB 3.2 Gen 2x2 Type-C (4 of 6): Port Port Mux / Redriver Coupling Capacitors..........................73 Figure 34: USB 3.2 Gen 2x2 Type-C (5 of 6): Type-C Power Delivery Controller.............................................74 Figure 35: USB 3.2 Gen 2x2 Type-C (6 of 6): Type-C Connector and Port Protection......................................75 Figure 36: USB4 on COM-HPC USB Port 2 (Fig 1 of 6): COM-HPC Side RX Coupling Caps.........................76 Figure 37: USB4 on COM-HPC USB Port 2 (Fig 2 of 6): Intel JHL8040R Thunderbolt Retimer Part 1............77 Figure 38: USB4 on COM-HPC USB Port 2 (Fig 3 of 6): Intel JHL8040R Thunderbolt Retimer Part 2............78 Figure 39: USB4 on COM-HPC USB Port 2 (Fig 4 of 6): Output Coupling and Protection...............................79 Figure 40: USB4 on COM-HPC USB Port 2 (Fig 5 of 6): Power Delivery Controller.........................................80 Figure 41: USB4 on COM-HPC USB Port 2 (Fig 6 of 6): Type-C Connector and USB Port Protector..............81 Figure 42: Boot SPI on Carrier (Example 1)......................................................................................................82 Figure 43: Boot SPI on Carrier ­ Socketed Flash and Multiplexer to External Programmer.............................85 Figure 44: eSPI Generic Interface Example: SIO, FPGA, LPC Bridge, or Other Peripheral eSPI Device........86 Figure 45: DisplayPort Over DDI........................................................................................................................87 Figure 46: HDMI Over DDI.................................................................................................................................90 Figure 47: eDP Schematic Example..................................................................................................................92

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Figure 48: eDP Connector Pin Numbering........................................................................................................93 Figure 49: MIPI-CSI...........................................................................................................................................95 Figure 50: MIPI SoundWire Routing Topologies................................................................................................98 Figure 51: MIPI SoundWire Point to Point Connection With SI Components....................................................98 Figure 52: UART0 and UART1 RS-232 Level Translated Asynchronous Serial Ports....................................101 Figure 53: I2C0 Example: Carrier EEPROM in S5 Power Domain..................................................................104 Figure 54: I2C0 Example: Carrier Temperature Sensor in S0 Power Domain.................................................105 Figure 55: Port 80h Debug Display Over COM-HPC USB_PD_I2C................................................................107 Figure 56: Carrier BMC with IPMB Link to Module ­ Sheet 1..........................................................................109 Figure 57: Carrier BMC with IPMB Link to Module ­ Sheet 2..........................................................................110 Figure 58: Carrier BMC with IPMB Link to Module ­ Sheet 3..........................................................................111 Figure 59: Module Type Detection / Protection ­ ATX Power Supply and Client Type Module / Carrier.........117 Figure 60: Module Type Detection / Protection ­ AT Power Supply and Server Type Module / Carrier..........117 Figure 61: PCB Cross Section Terms and Notations.......................................................................................120 Figure 62: Vendor Specific Heat Spreader to Module Attachment ­ Bottom Side Module PCB Access.........134 Figure 63: Heat Spreader Assembly Mounting to Carrier ­ Bottom Side Screw Access.................................135 Figure 64: Heat Spreader Assembly Mounting to Carrier ­ Top Side Screw Access......................................136 Figure 65: Heat Spreader Assembly Mounting to Carrier With Broaching Nut ­ Top Side Screw Access......137 Figure 66: Heat Spreader Assembly Mounting to Carrier and Chassis ­ Top Side Screw Access..................138 Figure 67: JSOM (Jack Screw Standoff ­ Micro) Diagram and Application Cutaway.....................................140 Figure 68: (a) Hex Nuts to Torque (b) Diagonal Torque Application / De-application (c) Hex Screw Turns....141 Figure 69: COM-HPC Stack Dis-assembly Procedure Using JSOM Hardware..............................................141 Figure 70: FEM Simulation Results ­ 0.0625" FR4 Carrier ­ No Stiffener......................................................142 Figure 71: Mechanical Carrier Stiffener Possibility..........................................................................................143 Figure 72: Carrier Board Stiffener Keep-Out Region (Seen Through Carrier).................................................144 Figure 73: Application Specific Part Number (ASP) Reference Guide............................................................145 Figure 74: Synchronous Ethernet Overview....................................................................................................147 Figure 75: Synchronous Ethernet Example Implementation...........................................................................148 Figure 76: Alternative eDP Example (Sheet 1 of 6): Passive Stuffing Options ­ eDP and DSI.......................151 Figure 77: Alternative eDP Example (Sheet 2 of 6): Backlight Control Options..............................................152 Figure 78: Alternative eDP Example (Sheet 3 of 6): Connector to Display Panel Assembly...........................153 Figure 79: Alternative eDP Example (Sheet 4 of 6): Backlight LED Driver......................................................154 Figure 80: Alternative eDP Example (Sheet 5 of 6): Split Rail (Pos / Neg) PS for AMOLED..........................155 Figure 81: Alternative eDP Example (Sheet 6 of 6): High Side Gate Driver for eDP Backlight.......................156 Figure 82: eSPI Header Example....................................................................................................................157

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1.

Preface

Preface

1.1.

About This Document

This document provides information for designing project specific Carrier Boards for systems using COMHPC Modules. This document is a design guide and not a specification document. It should be used by together with the COM-HPC Base Specification, with other industry specifications (listed in Section 1.9. below), with silicon and component vendor's documentation and with your COM-HPC Module vendor's product documentation.

The PICMG COM Express Carrier Board Design Guide is also a very useful additional source of information. The COM-HPC and COM Express pin names are not the same, but it is not hard to correlate them. The COM Express design guide document is available for free download on the public PICMG website (www.picmg.org). No membership is required to down load the design guides.

1.2.

Intended Audience

This design guide is intended for electronics engineers and PCB layout engineers designing Carrier Boards for PICMG COM-HPC Modules. It may also be useful to COM-HPC Module designers for them to better understand how COM-HPC Modules are used, and to understand how some of the design rules (trace length recommendations, trace length matching recommendations etc.) are shared between Module and Carrier designs.

1.3.

No Special Word Usage

Unlike a PICMG specification, which assigns special meanings to certain words such as "shall", "should" and "may", there is no such usage in this document. That is because this document is not a specification; it is a non-normative design guide.

1.4.

No Statements of Compliance

As this document is not a specification but a set of guidelines, there should not be any statements of compliance made with reference to this document.

1.5.

Correctness Disclaimer

The schematic examples given in this document are believed to be correct but no guarantee is given.

1.6.

Name and Logo Usage

The PCI Industrial Computer Manufacturers Group policies regarding the use of its logos and trademarks are as follows:

Permission to use the PICMG® organization logo is automatically granted to designated members only as stipulated on the most recent Membership Privileges document (available at www.picmg.org) during the period of time for which their membership dues are paid. Nonmembers may not use the PICMG® organization logo.

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Preface
The PICMG® organization logo must be printed in black or color as shown in the files available for download from the member's side of the Web site. Logos with or without the "Open Modular Computing Specifications" banner can be used. Nothing may be added or deleted from the PICMG® logo.
The use of the COM-HPC® logo is a privilege granted by the PICMG® organization to companies who have purchased the relevant specifications (or acquired them as a member benefit), and that believe their products comply with these specifications. Manufacturers' distributors and sales representatives may use the COMHPC® logo in promoting products sold under the name of the manufacturer. Use of the logos by either members or non-members implies such compliance. Only PICMG Executive and Associate members may use the PICMG® logo. PICMG® may revoke permission to use logos if they are misused. The COM-HPC® logo can be found on the PICMG web site, www.picmg.org.
The COM-HPC® logo must be used exactly as shown in the files available for download from the PICMG® Web site. The aspect ratios of the logos must be maintained, but the sizes may be varied. Nothing may be added to or deleted from the COM-HPC® logo.
The PICMG® name and logo and the COM-HPC® name and logo are registered trademarks of PICMG®. Registered trademarks must be followed by the ® symbol, and the following statement must appear in all published literature and advertising material in which the logo appears:
PICMG, the COM-HPC® name and logo and the PICMG logo are registered trademarks of the PCI Industrial Computers Manufacturers Group.

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Preface

1.7.

Intellectual Property

The PICMG Consortium draws attention to the fact that it is claimed that compliance with this specification may involve the use of a patent claim(s) ("IPR"). The PICMG Consortium takes no position concerning the evidence, validity or scope of this IPR.

The holder of this IPR has assured the Consortium that it is willing to license or sublicense all such IPR to those licensees (Members and non-Members alike) desiring to implement this specification. The statement of the holder of this IPR to such effect has been filed with the Consortium.

Attention is also drawn to the possibility that some of the elements of this specification may be the subject of IPR other than those identified below. The Consortium shall not be responsible for identifying any or all such IPR.

No representation is made as to the availability of any license rights for use of any IPR inherent in this specification for any purpose other than to implement this specification.

This specification conforms to the current PICMG® Intellectual Property Rights Policy and the Policies and Procedures for Specification Development and does not contain any known intellectual property that is not available for licensing under Reasonable and Non-discriminatory terms. In the course of Membership Review the following disclosures were made:

1.7.1.

Necessary IPR Claims (Referring to Mandatory or Recommended Features)

Samtec Inc. has the following patents, which may cover some aspects of the PICMG® COM-HPC® Module and Carrier Board Connectors. Contact Samtec Inc. at [email protected] for further information.
China 202111274151.2 China 201921051845.8 China 202030159171.5 EPO 007814686-0001 EPO 007814686-0002 EPO 007814686-0003 EPO 007814686-0004 EPO 19830502.1 Taiwan 109138672 Taiwan M589915 Taiwan D209464 Taiwan 109304816 US 29/709518

1.7.2.

Unnecessary Claims (Referring to Optional Features or Non-normative Elements)

US 9374900 CN 201480061913.2 TWM 505072
PCT 2021207390 TW 110112769
CN 11566924 US 17/817659

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Preface

1.7.3.

Third Party Disclosures

(Note that third party IPR submissions do not contain any claim of willingness to license the IPR.)  US 10,404,014 B2, FCI USA LLC, Sep. 3, 2019, "STACKING ELECTRICAL CONNECTOR WITH REDUCED CROSS TALK"

Refer to PICMG® IPR Policies and Procedures and the company owner of the patent for terms and conditions of usage.
PICMG® makes no judgment as to the validity of these claims or the licensing terms offered by the claimants.
THIS SPECIFICATION IS BEING OFFERED WITHOUT ANY WARRANTY WHATSOEVER, AND IN PARTICULAR, ANY WARRANTY OF NON-INFRINGEMENT IS EXPRESSLY DISCLAIMED. ANY USE OF THIS SPECIFICATION SHALL BE MADE ENTIRELY AT THE IMPLEMENTER'S OWN RISK, AND NEITHER THE CONSORTIUM, NOR ANY OF ITS MEMBERS OR SUBMITTERS, SHALL HAVE ANY LIABILITY WHATSOEVER TO ANY IMPLEMENTER OR THIRD PARTY FOR ANY DAMAGES OF ANY NATURE WHATSOEVER, DIRECTLY OR INDIRECTLY, ARISING FROM THE USE OF THIS SPECIFICATION.
Compliance with this specification does not absolve manufacturers of COM-HPC® equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.).
PICMG®, CompactPCI®, AdvancedTCA®, ATCA®, AdvancedMC®, CompactPCI® Express, COM Express®, COM-HPC®, MicroTCA®, SHB Express®, and the PICMG, CompactPCI, AdvancedTCA, µTCA and ATCA logos are registered trademarks, and xTCATM, IRTMTM and the IRTM logo are trademarks of the PCI Industrial Computer Manufacturers Group. All other brand or product names may be trademarks or registered trademarks of their respective holders.

1.7.4.

Copyright Notice

© 2021, 2022, 2023 PICMG. All rights reserved. All text, pictures and graphics are protected by copyrights. No copying is permitted without written permission from PICMG.
PICMG has made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied "as-is".

1.7.5.

Trademarks

Intel is a registered trademark of Intel Corporation. PCI Express is a registered trademark of Peripheral Component Interconnect Special Interest Group (PCI-SIG). COM-HPC® is a registered trademark of PCI Industrial Computer Manufacturers Group (PICMG). I2C is a registered trademark of NXP Semiconductors. Samtec is a registered trademark of Samtec Inc. All product names and logos referenced in this document are property of their owners. Thunderbolt is a registered trademark of the Intel corporation. Accelerate is a trademark of Samtec Inc.

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Preface

1.8.

Acronyms, Abbreviations and Definitions Used

Table 1: Acronyms, Abbreviations and Definitions Used

Term 10GBASE-KR
25GBASE-KR AC Coupled
ACPI AMOLED ARM ATX BIDIR BIOS BMC Carrier Board CCC DDI DIMM DisplayPort DP
DPLL DRAM DVI
EAPI EC ECN EEPROM Embedded DisplayPort eDP ESD eSPI FAE Flash FPGA FR4 Gb GbE Gbps GPI GPS GPIO GPO GPU

Definition 10 Gbps internal copper interface. Operates over a single lane and uses the same physical layer coding (defined in IEEE 802.3 Clause 49) as 10GBASE-LR (Single Mode Fiber 1310 nm ) / ER (Single Mode Fiber 1550 nm) /SR (Multi Mode Fiber 850 nm) 25 Gb/s internal copper interface using 25GBASE-R encoding over one lane in each direction This term means that series capacitors are inserted in the differential pair lines. This allows the transmit and receive lines to have their own, possibly separate DC common mode voltages. Advanced Configuration Power Interface Active Matrix Organic (semiconductor) Light Emitting Diode (a flat panel display technology) Advanced RISC Machine ­ a low power alternative CPU architecture widely used in mobile and embedded systems Advanced Technology Extended ­ Industry standard PC Motherboard form factor and power supply definitions Bidirectional (in reference to electrical signals) Basic Input Output System Baseboard Management Controller or Board Management Controller ­ located on Carrier for COM-HPC, if implemented An application specific circuit board that accepts a COM-HPC Module Current Carrying Capability Digital Display Interface ­ an interface that can serve DisplayPort and HDMI/DVI, Dual In-line Memory Module ­ larger format SDRAM memory module used in desk top systems and server PCs DisplayPort is a digital display interface standard put forth by the Video Electronics Standards Association (VESA). It defines a new license free, royalty free, digital audio/video interconnect, intended to be used primarily between a computer and its display monitor. Digital Phase Locked Loop Dynamic Random Access Memory Digital Visual Interface - a Digital Display Working Group (DDWG) standard that defines a standard video interface supporting both digital and analog video signals. The digital signals use TMDS. Embedded Application Programming Interface Embedded Controller Engineering Change Notice Electrically Erasable Programmable Read-Only Memory Embedded DisplayPort (eDP) is a digital display interface standard defined by the Video Electronics Standards Association (VESA) for digital interconnect of Audio and Video within a closed system such as a laptop computer or a piece of laboratory instrumentation. Electro Static Discharge Enhanced Serial Peripheral Interface Field Application Engineer EEPROM memory used for code storage. It can be updated in place ("flashed"). Field Programmable Gate Array A type of fiber-glass laminate commonly used for printed circuit boards. Gigabit Gigabit Ethernet Gigabits per second General Purpose Input Global Positioning System General Purpose Input Output General Purpose Output Graphics Processing Unit

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Term Gtps, GT/sec HDA
HDMI I2C
I2S I3C IPMB IPMI IPR LAN Legacy Device
LPC
LS M.2
MAC
MAFS MDI MDIO
ME
MIPI MMC
MS NA or N/A NBASE-KR NBASE-T
NC NDA Nyquist Frequency NVME
OCXO OEM OTP
PC-AT
PCB PCI

Definition
Giga Transfers per Second
Intel High Definition Audio (HD Audio) refers to the specification released by Intel in 2004 for delivering high definition audio.
High Definition Multimedia Interface ­ digital display interface widely used in consumer electronics such as digital TVs
Inter Integrated Circuit ­ 2 wire (clock and data) signaling scheme allowing communication between integrated circuits, primarily used to read and load register values.
Inter IC Sound ­ a 5 wire serial data interface, used primarily for transmitting and receiving digital audio data
Improved Inter Integrated Ciruit ­ builds on I2C and offers higher speeds and in-band interrupts
Intelligent Platform Management Bus
Intelligent Platform Management Interface
Intellectual Property Rights
Local Area Network
Relics from the PC-AT computer that are not in use in contemporary PC systems: primarily the ISA bus, UART-based serial ports, parallel printer ports, PS-2 keyboards, and mice. Definitions vary as to what constitutes a legacy device. Some definitions include IDE as a legacy device.
Low Pin-Count Interface: a low speed interface used for peripheral circuits such as Super I/O controllers, which typically combine legacy-device support into a single IC.
Least Significant
A small form factor add in card, for storage, WiFi, Cell Modems, etc. Interface options include PCIe x1, x2 or x4, SATA, USB and asynchronous serial. The sandard is maintained by the PCI-SIG.
Media Access Control ­ in this document, MAC refers to to the physical hardware bridge device between a CPU interface such as PCIe, and a network interface such as MDI or 10GBASE-KR or many others. A PHY is needed between the MAC and the Ethernet physical layer
Term for Master Attached Flash Sharing where the Flash component is attached to the processor interface.
Media Dependent Interface between a Ethernet PHY and the system magnetics and copper twisted pairs
Management Data Input/Output, or MDIO, is a 2-wire serial bus that is used to manage PHYs or physical layer devices in media access controllers (MACs).
Management Engine ­ Intel term for a management microcontroller embedded into the chipset silicon. It is active before the main x86 CPU boots.
Industry trade group that sets standards for mobile devices
Module Management Controller ­ a small microcontroller on the Module that works in conjunction with a Carrier BMC to implement IPMI functions. Implementation is optional.
Most Significant
Not Available, Not Applicable
Ethernet back plane signaling on PCB differential pairs. `N' signifies the speed ­ 25Gbps or 10Gbps
Ethernet physical layer signaling on twisted pairs. `N' signifies the speed ­ 10Gbps, 5Gbps, 2.5Gbps, 1Gbps, 100Mbps or 10Mbps
No Connect
Non-Disclosure Agreement
The critical frequency, sometimes called the "folding frequency", for a digital sampling system. It is (usually) ½ of the maximum data rate for the system.
Non Volatile Memory Express - non volatile memory with a PCIe interface ­ x1, x2 or x4 ­ often in an M.2 card form factor
Oven Controlled Xtal (crystal) Oscillator
Original Equipment Manufacturer
One Time Programmable ­ an option offered by some silicon vendors to change IC parameters by programming or blowing device fuses once, before shipment.
"Personal Computer ­ Advanced Technology" ­ an IBM trademark term used to refer to Intel x86 based personal computers in the 1990s
Printed Circuit Board
Peripheral Component Interconnect

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Preface

Term PCI Express PCIe PEG PHY Pin-out Type
PMD POR PPS PTP PU PD Ra ROM
RSVD RTC S0, S1, S2, S3, S4, S5
SAFS SATA SDP SKU SGMII SMA
SMBus SOC SO-DIMM SPD SPI Super I/O
TFT
TMDS
TPM USB WDT XAUI XGMII XO

Definition Peripheral Component Interconnect Express ­ serialized point-to-point version of PCI

PCI Express Graphics

Physical layer device, usually used in the context of

A reference to one of eight COM Express® or COM-HPC definitions for the signals that appear on the COM Express® Module connector pins.

Physical Medium Dependent ­ the physical layer of computer network protocols

Plan of Record

Pulse Per Second (for Ethernet)

Precision Time Protocol (for Ethernet)

Pull Up Pull Down

A connection between a signal and a specified power rail, through a resistor

Roughness Average ­ a measure of surface roughness, expressed in units of length.

Read Only Memory ­ a legacy term ­ often the device referred to as a ROM can actually be written to, in a special mode. Such writable ROMs are sometimes called Flash ROMs. BIOS is stored in ROM or Flash ROM.

Reserved. If a pin is marked RSVD, nothing should be connected to it

Real Time Clock ­ battery backed circuit in PC-AT systems that keeps system time and date

System states describing the power and activity level

S0

Full power, all devices powered

S1

CPU powered, CPU and bus clocks off, not in common use

S2

S3 Suspend to RAM

System context stored in RAM; RAM is in standby

S4 Suspend to Disk

System context stored on disk

S5 Soft Off

Main power rail off, only standby power rail present

Term for Slave Attached Flash Sharing where the Flash component is attached behind a BMC component.

Serial Advanced Technology Attachment: serial-interface standard for hard disks

Software Definable Pin

Stock Control Unit (a part number for a specific stockable item)

Serial Gigabit Media Independent Interface

Sub Miniature type A ­ a small form factor circular connector used for miniature coax cables, for WiFi, GPS and Cell Modem antennas

System Management Bus ­ a 3 wire bus ­ clock, data and alert ­ based in I2C ­ for system management

System On Chip

Small Outline Dual In-line Memory Module ­ small form factor SDRAM module

Serial Presence Detect ­ refers to serial EEPROM on DRAMs that has DRAM Module configuration information

Serial Peripheral Interface

An integrated circuit, typically interfaced via the LPC or eSPI bus that provides legacy PC I/O functions including PS2 keyboard and mouse ports, serial and parallel port(s) and a floppy interface.

Thin Film Transistor ­ refers to technology used in active matrix flat-panel displays, in which there is one thin film transistor per display pixel.

Transition Minimized Differential Signaling - a digital signaling protocol between the graphics subsystem and display. TMDS is used for the DVI digital signals.

Trusted Platform Module, chip to enhance the security features of a computer system.

Universal Serial Bus

Watch Dog Timer.

10 Gbps Attachment Unit Interface.

10 Gbps Media Independent Interface

Xtal (crystal) Oscillator

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1.9.

Applicable Documents and Standards

The list below is a partial list of documents and standards applicable to COM-HPC®. Many of the standards
groups listed below (MIPI, PCI-SIG, USB, VESA etc.) have much more additional information available ­ ECNs, supplemental documents, test specifications, SI masks etc. These are too numerous to list here. Please explore the links below for additional documents that may be relevant.

 Advanced Configuration and Power Interface (ACPI) Specification Version 6.3, January 2019, Copyright © 2018, Unified Extensible Firmware Interface (UEFI) Forum, Inc. All rights reserved. https://uefi.org/specifications

 ATX Specification Version 2.2 © Intel Corp. 2004

 ATX12V Power Supply Design Guide, Version 2.2, March 2005 © Intel Corp.

 eSPI Enhanced Serial Peripheral Interface, Interface Base Specification Revision 1.0, Copyright © 2016, Intel Corporation. January 2016 https://downloadcenter.intel.com/download/27055/

 HDMI (High Definition Multimedia Interface) specifications. http://www.hdmi.org  High-Definition Multimedia Interface specification versions 1.3, 1.4b, 2.1  HDMI Alt Mode USB Type-C
 I2C Specifification  NXP UM10204 "I2C-bus specification and user manual"  Rev 7 October 1, 2021  http://www.nxp.com use NXP site search tool to locate UM10204

 IEEE standards http://www.ieee.org
 IEEE Std 802.3TM-2018 (Revision of IEEE Std 802.3-2015), IEEE Standard for Information technology, Telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements ­ Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications
 IEEE1588 - 2008. IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems, July 24, 2008, Copyright 2016

 Intelligent Platform Management Interface Specification Second Generation, v2.0, Document Revision 1.1, October 1, 2013 (c) Intel, Hewlett-Packard, NEC, Dell

 An E7 red-line markup version of this document, dated April 21 2015, is available ­ see https:// www.intel.com/content/www/us/en/servers/ipmi/ipmi-technical-resources.html

 Intel Low Pin Count (LPC) Interface Specification Revision 1.1, August 2002 Copyright © 2002 Intel Corporation. All rights reserved. https://www.intel.com/content/www/us/en/design/technologies-and-topics/low-pin-count-interface-specification.html

 MIPI Alliance specifications https://www.mipi.org

 MIPI CSI-2

Camera Serial Interface

 MIPI-CSI-3

Camera Serial Interface

 MIPI DSI

Display Serial Interface

 MIPI DSI-2

Display Serial Interface

 MIPI C-PHY

Physical layer spec for CSI-2 and DSI-2 (alternative)

 MIPI D-PHY

Physical layer spec for CSI-2 and DSI-2

 MIPI M-PHY

Physical layer spec for CSI-3

 MIPI Soundwire Serialized audio interface

 MIPI I3C

Two wire serial data interface, successor to I2C

 MXM Graphics Module Mobile PCI Express Module Electromechanical Specification Version 3.0 Revision 1.1 (c) 2009 Nvidia Corporation Note: this document is not publicly available at the time of this writing but it does exist

 NC-SI Network Controller Sideband Interface Specification http://www.dmtf.org/sites/default/files/standards/documents/DSP0222_1.0.0.pdf

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Preface
Document Number: DSP0222, Jul 21, 2009, Version: 1.0.0 Copyright© 2009 Distributed Management Task Force, Inc. (DMTF).
 NEBS (Network Equipment ­ Building Systems) This is a collection of documents describing reliability criteria for telecom equipment. The NEBs documents are maintained by Telcordia / Ericsson https://telecom-info.telcordia.com
 PCI-SIG (Peripheral Component Interconnect Special Interest Group) specifications https://www.pcisig.com  PCI Express Base Specification Revision 5.0  PCI Express Card Electromechanical Specification Revision 4.0  PCI Express Mini Card Electromechanical Specification Revision 2.1  Add USB 3.0 to the Mini Card  PCI Express M.2 Specification Revision 4.0 V1.0  PCI Local Bus Specification Revisions 3,4 and 5.
 PICMG (PCI Industrial Computer Manufacturing Group) documents http://www.picmg.org/  PICMG COM.0 COM Express Module Base Specification Revision 3.0  PICMG EAPI Embedded Application Software Interface Specification Revision 1.0  PICMG EEEP Embedded EEPROM Specification Revision 1.0 (for COM-Express)  PICMG COM-HPC EEEP Embedded EEPROM Specification Revision 1.0  PICMG COM-HPC Carrier Design Guide Revision 1.0  PICMG COM Express Carrier Design Guide Revision 2.0  PICMG COM-HPC Platform Management Interface Specification Revision 1.0  PICMG Policies and Procedures for Specification Development, Revision 2.0
 Serial ATA Revision 3.5a Specification (March 2021) http://www.sata-io.org/
 SFP+, SFF-8083 Rev 3.1, SFF-8083 Specification for SFP+ 1X 10 Gb/s Pluggable Transceiver Solution (SFP10) Rev 3.1, Sep. 13, 2014 ftp://ftp.seagate.com/sff/SFF-8083.PDF
 SGET (Standardization Group for Embedded Technologies) standards and documents (www.sget.org)
 SMARC Hardware Specification Revision 2.1.1 (Smart Mobility ARChitecture)
 SMARC Design Guide Revision 2.1.1
 SPI, Serial Peripheral Interface Bus See http://elm-chan.org/docs/spi_e.html for some general information on SPI
 System Management Bus (SMBus) Specification Version 2.0, August 3, 2000 Copyright © 1994, 1995, 1998, 2000 Duracell, Inc., Energizer Power Systems, Inc., Fujitsu, Ltd., Intel Corporation, Linear Technology Inc., Maxim Integrated Products, Mitsubishi Electric Semiconductor Company, PowerSmart, Inc., Toshiba Battery Co. Ltd., Unitrode Corporation, USAR Systems, Inc. see http://www.smbus.org
 Trusted Computing Group Specifications https://www.trustedcomputinggroup.org Trusted Platform Module (TPM), Trusted Computing Group Specification 1.2 Revision 103, July 9, 2007 TPM 2.0 Library Specification
 Underwriters Laboratories UL 1642 Standard for Safety for Lithium Batteries
 USB Specifications https://www.usb.org/  USB 2.0  USB 3.0, 3.1, 3.2  USB4 also known as "Thunderbolt 4"  USB Type-C Connector and Power Delivery specifications
 VESA (Video Electronics Standards Association) https://www.vesa.org  DisplayPort Interoperability Guideline Version 1.1a, February 5, 2009 http://www.vesa.org/vesa-standards/free-standards/  DisplayPort Standard Version 1.4  DisplayPort Standard Version 2.0  Embedded DisplayPort (eDP) Specification Rev. 1.4b, Oct 10, 2015

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2.

COM-HPC Interfaces

COM-HPC Interfaces

2.1.

COM-HPC Client and Server Pinout Differences

The complete listings of signal descriptions and connector pin assignments for the COM-HPC Client and Server pinout types are found in the PICMG COM-HPC Module Base Specification and are not repeated here. Table 2 below details the Module connector pin assignments that differ between the Client and Server types.

Table 2:

Client and Server Type Pinout Difference Table

Pin Row Client

Server

20

A DDI1_SDA_AUX-

ETH4_RX-

21

A DDI1_SCL_AUX+

ETH4_RX+

23

A DDI1_PAIR0-

ETH5_RX-

24

A DDI1_PAIR0+

ETH5_RX+

26

A DDI1_PAIR1-

ETH6_RX-

27

A DDI1_PAIR1+

ETH6_RX+

29

A DDI1_PAIR2-

ETH7_RX-

30

A DDI1_PAIR2+

ETH7_RX+

32

A DDI1_PAIR3-

RSVD

33

A DDI1_PAIR3+

RSVD

35

A eDP_AUX-

ETH4_TX-

36

A eDP_AUX+

ETH4_TX+

38

A eDP_TX0-

ETH5_TX-

39

A eDP_TX0+

ETH5_TX+

41

A eDP_TX1-

ETH6_TX-

42

A eDP_TX1+

ETH6_TX+

44

A eDP_TX2-

ETH7_TX-

45

A eDP_TX2+

ETH7_TX+

47

A eDP_TX3-

USB1_AUX-

48

A eDP_TX3+

USB1_AUX+

19

B I2S_LRCLK/SNDW_CLK3 RSVD

20

B I2S_DOUT/SNDW_DAT3 RSVD

21

B I2S_MCLK

RSVD

22

B I2S_DIN/SNDW_DAT2

RSVD

23

B I2S_CLK/SNDW_CLK2

RSVD

45

B LID#

RSVD

46

B SLEEP#

RSVD

20

C SNDW_DMIC_CLK1

ETH0_TX-

21

C SNDW_DMIC_DAT1

ETH0_TX+

23

C SNDW_DMIC_CLK0

ETH1_TX-

24

C SNDW_DMIC_DAT0

ETH1_TX+

26

C DDI0_DDC_AUX_SEL

ETH2_TX-

27

C DDI1_DDC_AUX_SEL

ETH2_TX+

28

C DDI0_HPD

GND

29

C DDI1_HPD

ETH3_TX-

30

C eDP_HPD

ETH3_TX+

31

C eDP_VDD_EN

GND

32

C eDP_BKLT_EN

USB3_SSRX-

33

C eDP_BKLTCTL

USB3_SSRX+

35

C USB1_AUX-

USB2_SSRX-

36

C USB1_AUX+

USB2_SSRX+

19

D DDI0_SDA_AUX-

ETH0_RX-

20

D DDI0_SCL_AUX+

ETH0_RX+

22

D DDI0_PAIR0-

ETH1_RX-

23

D DDI0_PAIR0+

ETH1_RX+

25

D DDI0_PAIR1-

ETH2_RX-

26

D DDI0_PAIR1+

ETH2_RX+

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Pin Row Client

28

D DDI0_PAIR2-

29

D DDI0_PAIR2+

31

D DDI0_PAIR3-

32

D DDI0_PAIR3+

34

D AC_PRESENT

35

D RSVD

3

E DDI2_SDA_AUX-

4

E DDI2_SCL_AUX+

6

E DDI2_PAIR0-

7

E DDI2_PAIR0+

9

E DDI2_PAIR1-

10

E DDI2_PAIR1+

12

E DDI2_PAIR2-

13

E DDI2_PAIR2+

15

E DDI2_PAIR3-

16

E DDI2_PAIR3+

18

E DDI2_DDC_AUX_SEL

19

E DDI2_HPD

69

E RSVD

70

E RSVD

71

E RSVD

72

E RSVD

73

E RSVD

74

E RSVD

75

E RSVD

76

E RSVD

77

E RSVD

78

E NBASET1_CTREF

79

E NBASET1_SDP

80

E NBASET1_LINK_MID#

81

E NBASET1_LINK_ACT#

82

E NBASET1_LINK_MAX#

84

E RSVD

85

E RSVD

87

E ETH0_RX-

88

E ETH0_RX+

90

E ETH1_RX-

91

E ETH1_RX+

1

F RSVD

2

F RSVD

3

F RSVD

4

F RSVD

5

F RSVD

6

F RSVD

7

F RSVD

8

F RSVD

9

F RSVD

10

F RSVD

11

F RSVD

12

F RSVD

13

F RSVD

14

F RSVD

68

F RSVD

69

F RSVD

71

F NBASET1_MDI0-

72

F NBASET1_MDI0+

74

F NBASET1_MDI1-

75

F NBASET1_MDI1+

77

F NBASET1_MDI2-

78

F NBASET1_MDI2+

PICMG® COM-HPC® Carrier Design Guide

Server ETH3_RXETH3_RX+ USB3_SSTXUSB3_SSTX+ USB2_SSTXUSB2_SSTX+ RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PCIe48_TXPCIe48_TX+ GND PCIe49_TXPCIe49_TX+ GND PCIe50_TXPCIe50_TX+ GND PCIe51_TXPCIe51_TX+ GND PCIe52_TXPCIe52_TX+ PCIe53_TXPCIe53_TX+ PCIe54_TXPCIe54_TX+ PCIe55_TXPCIe55_TX+ ETH2_SDP ETH3_SDP ETH4_SDP ETH5_SDP ETH6_SDP ETH7_SDP ETH4-7_I2C_CLK ETH4-7_I2C_DAT ETH4-7_INT# ETH4-7_MDIO_CLK ETH4-7_MDIO_DAT ETH4-7_PHY_INT# ETH4-7_PHY_RST# ETH4-7_PRSNT# PCIe48_RXPCIe48_RX+ PCIe49_RXPCIe49_RX+ PCIe50_RXPCIe50_RX+ PCIe51_RXPCIe51_RX+

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Pin Row Client

80

F NBASET1_MDI3-

81

F NBASET1_MDI3+

83

F RSVD

84

F RSVD

86

F ETH0_TX-

87

F ETH0_TX+

88

F ETH1_TX-

90

F ETH1_TX+

95

F RSVD

96

F ETH0-1_PRSNT#

97

F ETH0-1_PHY_RST#

2

G GND

3

G USB2_SSRX0-

4

G USB2_SSRX0+

5

G GND

6

G USB2_SSRX1-

7

G USB2_SSRX1+

8

G GND

9

G USB3_SSRX0-

10

G USB3_SSRX0+

11

G GND

12

G USB3_SSRX1-

13

G USB3_SSRX1+

15

G USB3_LSRX

16

G USB3_LSTX

17

G USB2_LSRX

18

G USB2_LSTX

19

G PEG_LANE_REV#

69

G RSVD

70

G RSVD

72

G CSI0_RX0-

73

G CSI0_RX0+

75

G CSI0_RX1-

76

G CSI0_RX1+

78

G CSI0_RX2-

79

G CSI0_RX2+

81

G CSI0_RX3-

82

G CSI0_RX3+

84

G CSI0_CLK-

85

G CSI0_CLK+

87

G CSI0_I2C_CLK

88

G CSI0_I2C_DAT

89

G CSI0_MCLK

90

G CSI0_RST#

91

G CSI0_ENA

93

G RSVD

94

G RSVD

96

G ETH0-1_I2C_CLK

97

G ETH0-1_I2C_DAT

98

G ETH0-1_PHY_INT#

99

G ETH0-1_INT#

1

H GND

2

H USB2_SSTX0-

3

H USB2_SSTX0+

4

H GND

5

H USB2_SSTX1-

6

H USB2_SSTX1+

7

H GND

8

H USB3_SSTX0-

9

H USB3_SSTX0+

PICMG® COM-HPC® Carrier Design Guide

Server PCIe52_RXPCIe52_RX+ PCIe53_RXPCIe53_RX+ PCIe54_RXPCIe54_RX+ PCIe55_RXPCIe55_RX+ PCIe_CLKREQ3# ETH0-3_PRSNT# ETH0-3_PHY_RST# RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PCIe56_RXPCIe56_RX+ PCIe57_RXPCIe57_RX+ PCIe58_RXPCIe58_RX+ PCIe59_RXPCIe59_RX+ PCIe60_RXPCIe60_RX+ PCIe61_RXPCIe61_RX+ PCIe62_RXPCIe62_RX+ GND PCIe63_RXPCIe63_RX+ PCIe_REFCLK3PCIe_REFCLK3+ ETH0-3_I2C_CLK ETH0-3_I2C_DAT ETH0-3_PHY_INT# ETH0-3_INT# RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

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Pin Row Client

10

H GND

11

H USB3_SSTX1-

12

H USB3_SSTX1+

13

H GND

14

H USB2_AUX-

15

H USB2_AUX+

16

H GND

17

H USB3_AUX-

18

H USB3_AUX+

68

H RSVD

69

H RSVD

71

H CSI1_RX0-

72

H CSI1_RX0+

74

H CSI1_RX1-

75

H CSI1_RX1+

77

H CSI1_RX2-

78

H CSI1_RX2+

80

H CSI1_RX3-

81

H CSI1_RX3+

83

H CSI1_CLK-

84

H CSI1_CLK+

86

H CSI1_I2C_CLK

87

H CSI1_I2C_DAT

88

H CSI1_MCLK

89

H CSI1_RST#

90

H CSI1_ENA

98

H ETH0-1_MDIO_CLK

99

H ETH0-1_MDIO_DAT

Server RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PCIe56_TXPCIe56_TX+ PCIe57_TXPCIe57_TX+ PCIe58_TXPCIe58_TX+ PCIe59_TXPCIe59_TX+ PCIe60_TXPCIe60_TX+ PCIe61_TXPCIe61_TX+ PCIe62_TXPCIe62_TX+ GND PCIe63_TXPCIe63_TX+ ETH0-3_MDIO_CLK ETH0-3_MDIO_DAT

COM-HPC Interfaces

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Reference Schematics and Block Diagrams

3.

Reference Schematics and Block Diagrams

3.1.

Sources for Technical Materials

The schematic diagrams, block diagrams and mechanical diagrams in this document were contributed by several companies and organizations, including Adlink, Advantech, Avnet Integrated, Bielefeld University, congatec, Intel, Kontron, Samtec and SECO. Hence the graphic styles vary a bit. An effort has been made to provide part numbers in the drawings that can be located in a web search (except for small generic parts).

3.2.

Schematic Conventions

Schematic examples are drawn with signal directions shown per the Figure below. Signals that connect directly to the COM-HPC connector are flagged with the text "COM" in the off-page connect symbol, as shown in Figure 1 below. Nets that connect to the COM-HPC Module are named per the PICMG COM-HPC specification in almost all cases.

Figure 1: Schematic Conventions

Output from IC

Output from IC

Input to IC

Input to IC

Bidir Signal

Bidir Signal

IC

Output from IC to Module

Output from IC to Module

Input to IC from Module

Input to IC from Module

Bidir Signal to / from Module

Bidir Signal to / from Module

Power nets shown in the sample schematics and drawings are labeled, for the most part, per the Table below. The power rail behavior under the various system power states is shown in the Table.

Table 3: Power Net Naming

Power Net

S0

On

+12V_S +5V_S +3.3V_S +1.5V_S +2.5V_S +5V_A +3.3V_A VCC_RTC

12V 5V 3.3V 1.5V 2.5V 5V 3.3V 3.0V

S3

S4

S5

Suspend to Suspend to Soft Off

RAM

Disk

off

off

off

off

off

off

off

off

off

off

off

off

off

off

off

5V

5V

5V

3.3V

3.3V

3.3V

3.0V

3.0V

3.0V

G3 Mechanical Off
off off off off off off off 3.0V

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Reference Schematics and Block Diagrams

3.3.

Ethernet NBASE-T

A typical NBASE-T implementation is shown in Figure 2 below. The "N" refers to the link speed, and may be 10 Mbps, 100 Mbps, 1 Gbps, 2.5 Gbps, 5 Gbps or 10 Gbps. However not all speeds may be available on all Module designs. All COM-HPC Modules are required to support at least the 1 Gbps rate.

This example shows a "Mag-Jack" (an 8 pin RJ45 jack with integrated isolation magnetics) from Wurth Electronics, p/n 7499611420. This part is claimed by Wurth to support 10 Mbps, 100 Mbps, 1 Gbps and 10 Gbps data rates. There are many similar parts from Wurth and from vendors such as Bel-Fuse, Pulse Electronics and others. It may be advisable to check with your Module vendor on the suitablity of chosen parts. Ethernet RJ45 jacks (including Mag-Jacks and jacks that require external magnetics) come in "tab-up" and "tab-down" versions. The Wurth part shown here is "tab-up". If a "tab-down" part is used then the PCB layout is impacted as the pin orientation is effectively flipped 180 degrees.

Implementing magnetics that are external to the jack is of course possible but it is trickier. It may be necessary in certain situations that require a higher than normal isolation between the Ethernet magnetics primary and secondary sides. This can be the case in safety critical designs such as medical equipment.

The colors and meanings of the colors used for NBASE-T LEDs are not standardized in the industry. The scheme shown in the diagram below is suggested for COM-HPC but not required

The diagram below shows ESD protection diode arrays (Texas Instruments TPD4E02B04) protecting the NBASE-T differential pairs. Many similar parts are available from other vendors. Make sure the selected part has a suitably low pin capacitance. It is very important that the parts (D43 and D44 in the figure) are placed close to the connector and are routed in a "no stub" fashion. For example the net NBASET0+ in the figure should hit D43 pin 6 and continue under the D43 package to catch pin 5 and then on to the RJ45 connector. Pins may be swapped for easier routing, as long as the pairs are kept together and the no-stub routing is followed.

Figure 2: NBASE-T

NBASET0_MDI0+ NBASET0_MDI0NBASET0_MDI1+ NBASET0_MDI1NBASET0_MDI2+ NBASET0_MDI2NBASET0_MDI3+ NBASET0_MDI3-

COM COM COM COM COM COM COM COM

NBASET0_MDI0+ NBASET0_CT0
NBASET0_MDI0-
NBASET0_MDI1+ NBASET0_CT1
NBASET0_MDI1-
NBASET0_MDI2+ NBASET0_CT2
NBASET0_MDI2-
NBASET0_MDI3+ NBASET0_CT3
NBASET0_MDI3-

X37

8 7 9

D1+ CD1 D1-

3 1 2

D2+ CD2 D2-

4 6 5

D3+ CD3 D3-

11 12 10

D4+ CD4 D4-

+3.3V_A

LED2_GK LED2_GA

13 14

G

1

8

G/Y

LED1_YK LED1_GA/YA
LED1_GK

15 16 17

SH2 SH1

SH2 SH1

NBASET0_LA# C608
470p 0402 50V
NBASET0_LMAX# NBASET0_LMID#
C609 470p 0402 50V

WE_7499611420

R394

330R 0402

COM NBASET0_LINK_ACT#

R397 R398

330R 0402 330R 0402

COM NBASET0_LINK_MAX_SPEED# COM NBASET0_LINK_MID_SPEED#

C610 470p 0402 50V

D43 NBASET0_MDI0+ 6 NBASET0_MDI0- 7
8 NBASET0_MDI1- 9 NBASET0_MDI1+ 10

5 NBASET0_MDI0+ 4 NBASET0_MDI03 2 NBASET0_MDI11 NBASET0_MDI1+

TI_TPD4E02B04

D44

NBASET0_MDI2+ 6

5 NBASET0_MDI2+

NBASET0_MDI2- 7

4 NBASET0_MDI2-

8

3

NBASET0_MDI3- 9

2 NBASET0_MDI3-

NBASET0_MDI3+ 10

1 NBASET0_MDI3+

TI_TPD4E02B04

NBASET0_SDP

COM

1 2

1 2

X36 XMOLEX530470210

Note: Connection of Center Tap should be adjusted depending on Phy used on COM-HPC module. Schematic shown here should offer stuffing options for all common architectures (separated caps at center tap, individual center taps shorted, adjustable CT capcitor values)

NBASET0_CTREF COM
C607 1u 0603 25V

R393 DNI 0R 0402 NBASET0_CT0 R395 DNI 0R 0402 NBASET0_CT1 R396 DNI 0R 0402 NBASET0_CT2 R399 DNI 0R 0402 NBASET0_CT3

C611

C612

C613

C614

4x 100n 0402 25V

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Reference Schematics and Block Diagrams

3.4.

Ethernet KR and KR4

The Ethernet KR interfaces consist of a single TX pair and single RX pair. These pairs are capacitively coupled off of the COM-HPC Module ­ either on the Carrier board (for Module to PHY or Module to Module situations) or within the SFP assemblies.

Ethernet KR4 interfaces are comprised of four TX pairs and four RX pairs, capacitively coupled off of the COM-HPC Module, as per the KR interfaces.

In order to save pins, the side band signals for the 10G / 25G / 40G / 100G Ethernet KR interfaces are serialized on the Module silicon per an Intel convention known as CEI. This is an acronym for "Common Electrical Interface". The serialized CEI signals need to be deserialized on the Carrier Board. The block diagrams in this section describe which components are needed and what the functions of the deserialized nets are.

The Ethernet KR LED information is carried on one I2C bus per four Ethernet KR channels, known as a Quad. The I2C buses are named ETH0-3_I2C* (where the * indicates the final characters of the net name in that signal group) and ETH4-7_I2C* for the Server type. As the Client only supports 2 Ethernet channels, the group is named ETH0-1_I2C*.

There is one MDIO bus per Quad available to configure the PHYs on the Carrier Board. The MDIOs are named ETH0-3_MDIO* and ETH4-7_MDIO* for the Server type. As the Client only supports 2 Ethernet channels, the group is named ETH0-1_MDIO*.

The Reset and Interrupt signals also follow the same naming convention.

The SDP signals are more critical in timing and are available directly.

3.4.1.

Ethernet KR CEI Block Diagrams

Ethernet KR CEI concepts are illustrated in block diagram format in Figures 3 through 9 on the following pages. Many of the details of these implementations are vendor NDA protected. Some references to vendor document numbers for confidential material are listed after each Figure, if material is available. Designers interested in these materials need to contact the silicon vendors directly and work out the necessary NDAs.

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Figure 3: Intel SoC with CEI Boundary

Reference Schematics and Block Diagrams

Intel SoC
New
ETH(0..3)
ETH0-3_MDIO ETH_I2C_0
ETH_TIMESYNC0 ETH_TIMESYNC1 ETH_TIMESYNC2 ETH_TIMESYNC3
ETH_LED11 ETH_LED9
ETH_LED10
ETH(4..7)
ETH4-7_MDIO ETH_I2C_1
ETH_TIMESYNC4 ETH_TIMESYNC5 ETH_TIMESYNC6 ETH_TIMESYNC7
ETH_GPIO5 ETH_GPIO3 ETH_GPIO4

Connector
COM-HPC Serv er
ETH[0:3]
ETH0-3_MDIO ETH0-3_I2C ETH0_SDP ETH1_SDP ETH2_SDP ETH3_SDP
ETH0-3_PRSNT# ETH0-3_PHY_RST#
ETH0-3_INT# ETH0-3_PHY_INT#
ETH[4:7]
ETH4-7_MDIO ETH4-7_I2C ETH4_SDP ETH5_SDP ETH6_SDP ETH7_SDP
ETH4-7_PRSNT# ETH4-7_PHY_RST#
ETH4-7_INT# ETH4-7_PHY_INT#

CEI0 Boundary CEI_PMD_L[0:3] CEI_ADDR0=0 CEI_ADDR1=1 CEI_ADDR2=0
CEI_MDIO CEI_I2C
CEI_PRSNT# CEI_RESET#
CEI_INT# CEI1 Boundary CEI_PMD_L[4:7] CEI_ADDR0=1 CEI_ADDR1=1 CEI_ADDR2=0 CEI_MDIO
CEI_I2C
CEI_PRSNT# CEI_RESET#
CEI_INT#

For further details on this configuration, refer to NDA protected Intel documents 620640 and 631178.

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Figure 4: Intel CEI 4x SFP28

Reference Schematics and Block Diagrams

Connector
COM-HPC Serv er
ETH[0:3]

CEI0 Boundary
CEI_PMD_L[0:3] CEI_ADDR0=0 CCEEII__AADDDDRR12==10

ETH0-3_MDIO ETH0-3_I2C ETH0_SDP ETH1_SDP ETH2_SDP ETH3_SDP
ETH0-3_PRSNT# ETH0-E3T_HP0H-Y3__RINSTT## ETH0-3_PHY_INT#
ETH[4:7]
ETH4-7_MDIO ETH4-7_I2C ETH4_SDP ETH5_SDP ETH6_SDP ETH7_SDP
ETH4-7_PRSNT# ETH4-7_PHY_RST#
ETH4-7_INT# ETH4-7_PHY_INT#

CEI_MDIO CEI_I2C
CEI_PRSNT# CEIC_ERIE_SINETT## CEI1 Boundary CEI_PMD_L[4:7] CEI_ADDR0=1 CEI_ADDR1=1 CEI_ADDR2=0
CEI_MDIO CEI_I2C
CEI_PRSNT# CEI_RESET#
CEI_INT#

PCA9546A MUX

I2C
Addr = 0xE0/0xE1
ResetN

I2C0 I2C1 I2C2 I2C3

EE PROM

I2C

WP

Addr = 0xA8/0xA9

PCA9575 I/O

I2C ResetN IntN
Addr = 0x40/0x41

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

PCA9685 LED

I2C EX TCL K OE n
Addr = 0x80/0x81

LE D0 LE D1
LE D2 LE D3 LE D4 LE D5 LE D6 LE D7 LE D8 LE D9 LE D10
LE D11 LE D12
LE D13 LE D14 LE D15

P0_SPD_A_LED P0_SPD_B_LED P0_ACT_LED P1_SPD_A_LED P1_SPD_B_LED P1_ACT_LED P2_SPD_A_LED P2_SPD_B_LED P2_ACT_LED P3_SPD_A_LED P3_SPD_B_LED P3_ACT_LED

This configuration is not supported by additional Intel documentation at the time of this writing.

PMD SFP_0
I2C RX_Loss ModPresN RS
PMD SFP_1
I2C RX_Loss ModPresN RS
PMD SFP_2
I2C RX_Loss ModPresN RS
PMD SFP_3
I2C RX_Loss ModPresN RS

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Figure 5: Intel CEI 4x SFP28 with Retimer C827/XL827

Reference Schematics and Block Diagrams

Connector
COM-HPC Serv er
ETH[0:3]
ETH0-3_MDIO ETH0-3_I2C ETH0_SDP ETH1_SDP ETH2_SDP ETH3_SDP
ETH0-3_PRSNT# ETH0-3_PHY_RST#
ETH0-3_INT# ETH0-3_PHY_INT#
ETH[4:7]
ETH4-7_MDIO ETH4-7_I2C ETH4_SDP ETH5_SDP ETH6_SDP ETH7_SDP
ETH4-7_PRSNT# ETH4-7_PHY_RST#
ETH4-7_INT# ETH4-7_PHY_INT#

CEI0 Boundary CEI_PMD_L[0:3]
CEI_ADDR0=0 CEI_ADDR1=1 CEI_ADDR2=0
CEI_MDIO CEI_I2C
CEI_PRSNT# CEI_RESET#
CEI_INT# CEI1 Boundary CEI_PMD_L[4:7] CEI_ADDR0=1 CEI_ADDR1=1 CEI_ADDR2=0
CEI_MDIO CEI_I2C
CEI_PRSNT# CEI_RESET#
CEI_INT#

PCA9546A MUX

I2C
Addr = 0xE0/0xE1
ResetN

I2C0 I2C1 I2C2 I2C3

EE PROM

I2C

WP

Addr = 0xA8/0xA9

C827/XL827

Parkvale

PMD(0..3)

PMD0

Addr0 Addr1 Addr2 Addr3 Addr4=0

PMD1 PMD2

MDI O ResetN IntN

PMD3

PCA9575 I/O

I2C ResetN IntN
Addr = 0x40/0x41

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

PCA9685 LED

I2C EX TCL K OE n
Addr = 0x80/0x81

LE D0 LE D1 LE D2 LE D3
LE D4 LE D5 LE D6 LE D7
LE D8 LE D9 LE D10 LE D11 LE D12
LE D13 LE D14 LE D15

For further details on this configuration, refer to NDA Intel document 636564.

P0_SPD_A_LED P0_SPD_B_LED P0_ACT_LED P1_SPD_A_LED P1_SPD_B_LED P1_ACT_LED P2_SPD_A_LED P2_SPD_B_LED P2_ACT_LED P3_SPD_A_LED P3_SPD_B_LED P3_ACT_LED P0_DISABLE P1_DISABLE P2_DISABLE P3_DISABLE

PMD SFP_0
I2C RX_Loss ModPresN RS
PMD SFP_1
I2C RX_Loss ModPresN RS
PMD SFP_2
I2C RX_Loss ModPresN RS
PMD SFP_3
I2C RX_Loss ModPresN RS

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Figure 6: Intel CEI QSFP28 with Retimer C827/XL827

Reference Schematics and Block Diagrams

Connector
COM-HPC Serv er
ETH[0:3]
ETH0-3_MDIO ETH0-3_I2C

CEI0 Boundary CEI_PMD_L[0:3] CEI_ADDR0=0 CEI_ADDR1=1 CEI_ADDR2=0
CEI_MDIO
CEI_I2C

C827/XL827 Parkvale
PMD(0..3) PMD(0..3)
Addr0 Addr1 Addr2 Addr3 Addr4=0
MDI O ResetN IntN

QSFP
PMD(0..3)
I2C
ResetN IntN Prese nt N LP Mo de

ETH0_SDP ETH1_SDP ETH2_SDP ETH3_SDP ETH0-3_PRSNT# ETH0-E3T_HP0H-Y3__RINSTT## ETH0-3_PHY_INT#
ETH[4:7]
ETH4-7_MDIO

CEI_PRSNT# CEIC_ERIE_SINETT##
CEI1 Boundary CEI_PMD_L[4:7] CCEEII__AADDDDRR01==11 CEI_ADDR2=0
CEI_MDIO

EE PROM

I2C

WP

Addr = 0xA8/0xA9

PCA9575 I/O

I2C ResetN IntN
Addr = 0x40/0x41

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

PCA9685 LED

ETH4-7_I2C ETH4_SDP ETH5_SDP ETH6_SDP ETH7_SDP
ETH4-7_PRSNT# ETH4-7_PHY_RST#
ETH4-7_INT# ETH4-7_PHY_INT#

CEI_I2C
CEI_PRSNT# CEI_RESET#
CEI_INT#

I2C EX TCL K OE n
Addr = 0x80/0x81

LE D0 LE D1 LE D2 LE D3 LE D4 LE D5 LE D6 LE D7 LE D8 LE D9 LE D10 LE D11 LE D12 LE D13 LE D14 LE D15

For further details on this configuration, refer to NDA Intel document 636566.

P0_SPD_A_LED P0_SPD_B_LED P0_ACT_LED P1_SPD_A_LED P1_SPD_B_LED P1_ACT_LED P2_SPD_A_LED P2_SPD_B_LED P2_ACT_LED P3_SPD_A_LED P3_SPD_B_LED P3_ACT_LED P0_DISABLE P1_DISABLE P2_DISABLE P3_DISABLE

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Figure 7: Intel CEI 4x 10GBASE-T Copper PHY X557-AT4

Reference Schematics and Block Diagrams

Connector
COM-HPC Serv er
ETH[0:3]
ETH0-3_MDIO ETH0-3_I2C

CEI0 Boundary CEI_PMD_L[0:3] CEI_ADDR0=0 CEI_ADDR1=1 CEI_ADDR2=0
CEI_MDIO
CEI_I2C

X55 7-AT4

Coppervale

PMD(0..3)

MDI0_[0:3]

LE D_P0

Addr0 = 0

Addr1 = 0

MDI1_[0:3]

Ad dr2

LE D_P1

Addr3

Addr4

MDI2_[0:3]

LE D_P2

MDI O

Rese tN

MDI3_[0:3]

In tN

LE D_P3

ETH0_SDP ETH1_SDP ETH2_SDP ETH3_SDP ETH0-3_PRSNT# ETH0-3_PHY_RST# ETH0-3_INT# ETH0-3_PHY_INT#
ETH[4:7]
ETH4-7_MDIO

CEI_PRSNT# CEI_RESET#
CEI_INT#
CEI1 Boundary CEI_PMD_L[4:7] CEI_ADDR0=1 CEI_ADDR1=1 CEI_ADDR2=0
CEI_MDIO

EE PROM

I2C

WP

Addr = 0xA8/0xA9

PCA9575 I/O

I2C Rese tN In tN
Addr = 0x40/0x41

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

PCA9685 LED

ETH4-7_I2C ETH4_SDP ETH5_SDP ETH6_SDP ETH7_SDP
ETH4-7_PRSNT# ETH4-7_PHY_RST#
ETH4-7_INT# ETH4-7_PHY_INT#

CEI_I2C
CEI_PRSNT# CEI_RESET#
CEI_INT#

I2C EX TCL K OE n
Addr = 0x80/0x81

LE D0 LE D1 LE D2 LE D3 LE D4 LE D5 LE D6 LE D7 LE D8 LE D9 LE D10 LE D11 LE D12 LE D13 LE D14 LE D15

For further details on this configuration, refer to NDA Intel document 613899.

4x RJ-45
MDI0 10GBASE-T LE D_P0 MDI1_[0:3] LE D_P1 MDI2_[0:3] LE D_P2 MDI3_[0:3] LE D_P3
P0_SPD_A_LED P0_SPD_B_LED P0_ACT_LED P1_SPD_A_LED P1_SPD_B_LED P1_ACT_LED P2_SPD_A_LED P2_SPD_B_LED P2_ACT_LED P3_SPD_A_LED P3_SPD_B_LED P3_ACT_LED P0_DISABLE P1_DISABLE P2_DISABLE P3_DISABLE

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Figure 8: Intel CEI 4x 1GBASE-T Copper PHY Marvell 88E1543

Reference Schematics and Block Diagrams

Connector
COM-HPC Serv er
ETH[0:3]
ETH0-3_MDIO ETH0-3_I2C

CEI0 Boundary CEI_PMD_L[0:3] CEI_ADDR0=0 CEI_ADDR1=1 CEI_ADDR2=0
CEI_MDIO
CEI_I2C

88E1543 Alaska
PMD(0..3) MDI0_[0:3]

MDI1_[0:3]

MDI O Rese tN IntN

MDI2_[0:3] MDI3_[0:3]

ETH0_SDP ETH1_SDP ETH2_SDP ETH3_SDP ETH0-3_PRSNT# ETH0-3_PHY_RST# ETH0-3_INT# ETH0-3_PHY_INT#
ETH[4:7]
ETH4-7_MDIO

CEI_PRSNT# CEI_RESET#
CEI_INT#
CEI1 Boundary CEI_PMD_L[4:7] CEI_ADDR0=1 CEI_ADDR1=1 CEI_ADDR2=0
CEI_MDIO

EE PROM

I2C

WP

Addr = 0xA8/0xA9

PCA9575 I/O

I2C ResetN IntN
Addr = 0x40/0x41

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

PCA9685 LED

ETH4-7_I2C ETH4_SDP ETH5_SDP ETH6_SDP ETH7_SDP
ETH4-7_PRSNT# ETH4-7_PHY_RST#
ETH4-7_INT# ETH4-7_PHY_INT#

CEI_I2C
CEI_PRSNT# CEI_RESET#
CEI_INT#

I2C EX TCL K OE n
Addr = 0x80/0x81

LE D0 LE D1 LE D2 LE D3 LE D4 LE D5 LE D6 LE D7 LE D8 LE D9 LE D10 LE D11 LE D12 LE D13 LE D14 LE D15

For further details on this configuration, refer to NDA Intel document 613900.

4x RJ-45
MDI0_[0:3] 1GBASE-T MDI1_[0:3] MDI2_[0:3] MDI3_[0:3]
P0_SPD_A_LED P0_SPD_B_LED P0_ACT_LED P1_SPD_A_LED P1_SPD_B_LED P1_ACT_LED P2_SPD_A_LED P2_SPD_B_LED P2_ACT_LED P3_SPD_A_LED P3_SPD_B_LED P3_ACT_LED P0_DISABLE P1_DISABLE P2_DISABLE P3_DISABLE

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Figure 9: AMD SoC 4xSFP+ with CS4223 Retimer

Reference Schematics and Block Diagrams

AMD SoC
EP YC3000
ETH[0:3]

Connector
COM-HPC Serv er
ETH[0:3]

SMBus INTy# PL TRS T# INTx#

ETH0-3_MDIO
ETH0-3_I2C ETH0_SDP ETH1_SDP ETH2_SDP ETH3_SDP
ETH0-3_PRSNT# ETH0-3_PHY_INT# ETH0-3_PHY_RST#
ETH0-3_INT#

ETH[4:7]

ETH4-7_MDIO
ETH4-7_I2C ETH4_SDP ETH5_SDP ETH6_SDP ETH7_SDP

CEI0 Boundary CEI_PMD_L[0:3] CEI_ADDR0=0 CEI_ADDR1=1 CEI_ADDR2=0
CEI_MDIO
CEI_PRSNT# CEI_RESET#
CEI_INT# CEI1 Boundary CEI_PMD_L[4:7] CEI_ADDR0=1 CEI_ADDR1=1 CEI_ADDR2=0 CEI_MDIO

CS4223

PMD(0..3)

PMD0

Addr0 Addr1 Addr2 Addr3 Addr4=0 I2C

PMD1 PMD2

ResetN IntN

PMD3

PCA9545A MUX

I2C
Addr = 0xE0/0xE1
ResetN

I2C0 I2C1 I2C2 I2C3

PCA9555 I/O

I2C IntN
Addr = 0x40/0x41

P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P0.7
P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0

ETH4-7_PRSNT# ETH4-7_PHY_RST#
ETH4-7_INT# ETH4-7_PHY_INT#

CEI_PRSNT# CEI_RESET#

For further details on this configuration, contact AMD.

PMD SFP_0
I2C TX_Disable TX_Fault RX_Loss ModPresN
PMD SFP_1
I2C TX_Disable TX_Fault RX_Loss ModPresN
PMD SFP_2
I2C TX_Disable TX_Fault RX_Loss ModPresN
PMD SFP_3
I2C TX_Disable TX_Fault RX_Loss ModPresN

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3.4.2. Table 4:

PHY Addresses MDIO Addresses for Intel POR External PHYs

PHY Intel "Parkvale"
Intel "Coppervale" Marvell offers a similar Phy

MDIO Address (Decimal) 2 3 8 9 10 11 12 13 14 15

Reference Schematics and Block Diagrams
Ethernet Quad / Port Quad0 Quad1
Quad0 Port0 Quad0 Port1 Quad0 Port2 Quad0 Port3 Quad1 Port0 Quad1 Port1 Quad1 Port2 Quad1 Port3

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Reference Schematics and Block Diagrams

3.5. 3.5.1.

Serial ATA Cabled SATA

The COM-HPC pin-outs offer up to two SATA ports, designated SATA0 and SATA1. The implementation for a cabled interface is straightforward, as illustrated in Figure 10 below. No Carrier coupling capacitors are needed as they are specified to be present on the Module. The connections between the Module and the SATA connector are simple differential pairs. Some routing rules may be found in Section 4. below.
Two common connector styles used for cabled SATA implementations are shown in the Figure. The upper image shows a 7 pin data-only connector. Power to the SATA drive is handled separately in this case. The lower image in the Figure shows a 22 pin connector that handles SATA data and power. There are three power rails defined on this connector, but all three are not necessarily used. Smaller format drives tend to use just one or two of these rails, Check the drive specifications.
Figure 10 below shows two typical COM-HPC cabled SATA0 implementations. SATA1 is handled in the same way. Note how the data pair polarity order flips along the connector pins: TX+ TX- GND RX- RX+ ... this is not a mistake, but is part of the SATA specification.

5

4

Figure 10: Serial ATA - Cabled

D

SATA0_TX+ COM

SATA0_TX- COM

SATA0_RX- COM SATA0_RX+ COM

SATA1 PTH H1

1 2 3 4 5 6 7

TTGRRGGXXNXXNN-+D+-DD

H2 PTH LOTES_ABA-SAT-010-K21

3
SATA1_TX+ COM SATA1_TX- COM SATA1_RX- COM SATA1_RX+ COM

2

SATA2 PTH H1

1 2 3 4 5 6 7

TTGRRGGXXNXXNN-+D+-DD

H2 PTH LOTES_ABA-SAT-010-K21

C

+12V_S

+5V_S

B

+3.3V_S

SATA0_RX+ COM SATA0_RX- COM SATA0_TX- COM SATA0_TX+ COM
A

H3

H4

H1

H2

SATA1

P15 P14 P13 P12 P11 P10
P9 P8 P7 P6 P5 P4 P3 P2 P1

1GRG1GG1VVV2NSNNN22CCCVDVDDDVVCCCD GND VVVCCCCCC333

S7 S6 S5 S4 S3 S2 S1

GND TGRRXNXX-D-+ GTNXD+

MOLEX_47018-4001

PICMG® COM-HPC® Carrier Design Guide

5

4

+12V_S +5V_S
+3.3V_S

SATA1_RX+ SATA1_RX-

COM COM

SATA1_TX- COM SATA1_TX+ COM

3

H4

H2

SATA3

P15 P14 P13 P12 P11 P10
P9 P8 P7 P6 P5 P4 P3 P2 P1

1GRG1GG1VVV2NSNNN22CCCVDVDDDVVCCCD GND VVVCCCCCC333

S7 S6 S5 S4 S3 S2 S1

GND TGRRXNXX-D-+ GTNXD+

MOLEX_47018-4001

H1

H3

Rev. 2.1 / Aug 10, 2023 33/159
2

Reference Schematics and Block Diagrams

3.5.2.

mSATA SSDs

The SATA specification defines a small form factor card for SATA SSDs that is almost identical in mechanical and electrical definition to the PCI-SIG miniPCIe format. The same card connector and mounting holes are used. Both half size and full size cards are in use. Sometimes dual mini-PCIe / mSATA implementations are executed. This involves multiplexing four signals per the following Table:

Table 5: mSATA Pin Mapping Relative to miniPCIe

MiniPCIe Card Pin Name PETP0 PETN0 PERP0 PERN0

MiniPCIe / mSATA Card Pin Number 33 31 25 23

PCIE Signal Relative to COM-HPC Module PCIe TX+ PCIe TXPCIe RX+ PCIe RX-

SATA Signal Relative to COM-HPC Module SATA TX+ SATA TXSATA RXSATA RX+

The SATA_RX- mapping to miniPCIe PERP0 and SATA_RX+ to PERN0 is intentional per the SATA specification.
The signals do not have to be multiplexed if a mSATA only or miniPCIe only implementation is desired.
SSD implementations are largely moving away from the miniPCIe format and to M.2 formats. In the M.2 formats, there are PCIe interfaces defined (x1, x2 and x4) and a SATA interface defined, similar to the miniPCIe / mSATA pin sharing format shown in the Table above. The M.2 PCIe x 4 format, sometimes referred to as NVMe, offer a much higher interface bandwidth than mSATA.

3.5.3.

M.2 SATA SSDs

The PCI Express M.2 Specification defines several M.2 format SATA SSD options that may be used in COMHPC systems. These include (but are not limited to):
· Socket 2 B-M Key (Table 3-23 in the PCI-SIG Version 4.0 M.2 document)
· Socket 3 M Key (Table 3-28)
These are not diagrammed here as SATA SSD implementations seem to be losing ground to PCIe based SSD implementations.

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3.6. 3.6.1.

PCI Express General Notes

The COM-HPC PCIe resources are divided into 5 Groups:

Reference Schematics and Block Diagrams

· Group 0 Low ( 8 lanes)  Generally used for smaller links (x1, x2, x4) and slower PCIe link speeds (PCIe Gen 1,2,3).
· Group 0 High (8 lanes)  Recommended for use with one or two PCIe x4 NVME SSD instances  The COM-HPC specification recommends that higher bandwidth PCIe links be steered to this Group
· Group 1 (16 lanes)  Recommended for PEG use  The COM-HPC specification recommends that higher bandwidth PCIe links be steered to this Group
· Group 2 (16 lanes)  General purpose links ­ x16 or combinations of x8 and / or x4
· Group 3 (16 lanes)  Available on the Server pinout only

Each PCIe Group listed above has it's own 100 MHz PCIe Reference Clock pair from the COM-HPC Module. Additionally, there is a CLKREQ# (Clock Request) input to the Module for each PCIe Group.
There is one additional PCIe link available on both the Client and Server pinouts. This is a x1 link for use with a Carrier BMC (Board Management Controller). The BMC PCIe link makes use of the Group 0 PCIe Reference Clock pair.
If only a single PCIe link (of any link width ­ x1, x2, x4, x8 or x16) is used from a PCIe Group, then the COMHPC PCIe Reference Clock pair may be used directly with the link target. If a Group uses more than one link (i.e. 2 or more links) then a Carrier Board PCIe Reference Clock buffer is needed for that Group. Many PCIe clock buffer products are available on the market. Buffers with 2,4,6 or 8 and more output pairs are available. The buffer must be appropriate for the fastest PCIe link in the Group (PCIe Gen 3, 4 or 5). Several examples are shown in the schematics below.
If the link's PCIe target is located on a slot card or a mezzanine board such as an M.2 site, the connector involved must be rated for the fastest PCIe link in use for that target. At the time of this writing, most such connectors are PCIe Gen 3 capable. Gen 4 and Gen 5 capable connectors are becoming available, most visibly from Amphenol FCI.

PICMG® COM-HPC® Carrier Design Guide

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Reference Schematics and Block Diagrams

3.6.2.

PCI Express Coupling Capacitor Locations

The proper positions for PCIe data pair coupling capacitors is shown in Figure 11 below. · COM-HPC Module TX pair coupling caps are on the COM-HPC Module. · COM-HPC Module RX pair coupling caps are NOT on the COM-HPC Module.  For most Device Up mezzanine card implementations (Slot card, Mini-PCIe, and M.2 card) the coupling caps are up on the mezzanine card, close to the mezzanine target device TX pins.  The exception to this rule is with MXM-3 graphics cards: there are no PCIe coupling caps at all on a MXM-3 graphics card. The COM-HPC Module TX lines are AC coupled on the COMHPC Module. The COM-HPC Module RX lines are AC coupled on the Carrier, near the MXM-3 Module TX pins.  For Device Down implementations, the coupling caps are down on the Carrier board, close to the target device TX pins.

Figure 11: PCIe Data Line Coupling Capacitor Positions (MXM-3 Cards Excluded)

COM-HPC Module
TX+ TXRX+ RX-

Device Up

RX+ RXTX+ TX-

PCIe Add-in Device

Device Down

TX+ TXRX+ RX-

RX+ RXTX+ TX-

PCIe Add-in Device

Carrier Board

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3.6.3.

Reference Schematics and Block Diagrams
PCIe Group 0 Low Examples: Device Down, mini-PCIe, M.2 E-Key, M.2 B-Key

Figure 12: PCIe Device Down on Carrier ­ PCIe Group 0 Low ­ PCIe Lane 0

+3.3V_S SECTION 1 OF 4

WAKE0#

0ohms 1%
5.1Kohms 5.1Kohms 5.1Kohms

COM COM
5 5
5 R55 0402 R64 R65 R66

PCIe0_TX+ PCIe0_TX-
PCIe_CLK_G0L_0+ PCIe_CLK_G0L_0-
PCI_RESET_G0L_0# WAKE_G0L_1#
LAN1_SMB_SCL LAN1_SMB_SDA LAN1_SMB_ALERT#

24 PE_R+ 23 PE_R26 PECLK+ 25 PECLK17 PE_RST# 16 PE_WAKE# 34 SMB_CLK 36 SMB_DATA 35 SMB_ALRT#
i210

U9 PE_T+ 21 PE_T- 20
NC_SI_CLK_IN 2 NC_SI_CRS_DV 3
NC_SI_TX_EN 7 NC_SI_ARB_IN 43 NC_SI_ARB_OUT 44
NC_SI_TXD0 9 NC_SI_TXD1 8 NC_SI_RXD0 6 NC_SI_RXD1 5

This reference sheet does not show the full Intel WGI210T device but only shows the
PCIe, Wake, and Clocking interfaces

PE_i210_G0L_RX+
PE_i210_G0L_RXNCSI0_LAN_CLK NCSI0_LAN_CRS_DV NCSI0_LAN_TXEN
NCSI0_LAN_ARB_IN NCSI0_LAN_ARB_OUT
NCSI0_LAN_TXD[0] NCSI0_LAN_TXD[1]
NCSI0_LAN_RXD[0] NCSI0_LAN_RXD[1]

0.22uF 10V
0.22uF 10V

C44 0402 C45 0402

PCIe0_RX+ PCIe0_RX-

COM COM

To i210 Strapping Resistors

This figure shows a portion of an Intel i210 Gigabit Ethernet implementation, the portion that is relevant to the COM-HPC Module interface. This figure shows the interface to the COM-HPC and to some Carrier board circuit elements such as an appropriate PCIe Clock buffer, shown later in this section.
The key point of this Figure is that coupling caps (C44 and C45 in the Figure) are needed on the Carrier, for the Carrier target device TX pair pins. These are the PCIe RX lines for the Module. These Carrier coupling caps are to be placed close to the i210 device, in a symmetric manner consistent with high speed PCB design practices.
Coupling caps for COM-HPC PCIe TX lines are on the Module, and are never needed on a COM-HPC Carrier.
If the PCIe target device is a slot or mezzanine card, the coupling caps for the target device are on the slot or mezzanine card and not on the Carrier. - except for MXM graphics card implementations. This case is discussed in Section 3.6.7. below.

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Figure 13: Mini-PCIe Site ­ PCIe Group 0 Low ­ PCIe Lane 1

Reference Schematics and Block Diagrams

+3.3V_S

PCIe_CLK_G0L_1+ PCIe_CLK_G0L_1-

COM COM COM COM
COM COM

PCIe1_RX+ PCIe1_RX-

PCIe1_TX+ PCIe1_TX-

PCI_RESET_G0L_1#

PCIe_CLKREQ_G0L_1#

WAKE0#

R50 0402

USB4+ USB4-

PCIe_CLK_SDA PCIe_CLK_SCL

0ohms 1% 400mA 1
2 90R
R47 0402 R48 0402

L1 4
3 0805
0ohms 1% 0ohms 1%

1% 10Kohms
1% 10Kohms
1% 10Kohms

DNI 0402 R3
DNI 0402 R4 0402 R5

WAKE_G0L_2#
USB4_CMC_+ USB4_CMC_-

R42 0402

DNI

0ohms 1%

+3.3V_A

+3.3V_S_G0L_MPCIE

0ohms DNI R40

1%

0402

+3.3V_S

0ohms 1%

R41 0402

C31 0402 C30 0402 C42 0603

+3.3V_S_G0L_MPCIE +3.3V_S_G0L_MPCIE

0402 C29 0603 C41

50V 0.1uF
10V 22uF

0.1uF 50V
0.1uF 50V
22uF 10V

13 REFCLK+ 11 REFCLK-

25 PER0+ 23 PER0-

33 PET0+ 31 PET0-

22 PERST# 7 CLKREQ# 1 WAKE#

38 USB_D+ 36 USB_D-

32 SMB_DATA 30 SMB_CLK

46
NC
44
NC
42
NC

LED_WPAN# LED_WLAN# LED_WWAN#

20 W_DISABLE1# 51 W_DISABLE2#

16
NC
8
NC
14
NC
10
NC
12
NC

UIM_SPU UIM_PWR UIM_RESET UIM_DATA UIM_CLK

19
NC
17
NC

UIM_IC_D+ UIM_IC_D-

MINI-PCI-EXP

PCIE

UIM

J3

V_3V3_AUX_2 2

V_3V3_AUX_24 24

GND

V_3V3_AUX_39 39

V_3V3_AUX_41 41

V_3V3_AUX_52 52

V_1V5_6 6 V_1V5_28 28 V_1V5_48 48

+1.5V_S_G0L_MPCIE

0ohms 1%

C33 0402 C32 0402 C43 0603

0.1uF 50V
0.1uF 50V 22uF 10V

RESERVED_45 RESERVED_47 RESERVED_49

45 NC
47 NC
49 NC

GND
COEX1 3 NC COEX2 5 NC

MTG1 MTG2

53 NC
54 NC

GND_4 4 GND_9 9 GND_15 15 GND_18 18 GND_21 21 GND_26 26 GND_27 27 GND_29 29 GND_34 34 GND_35 35 GND_37 37 GND_40 40 GND_43 43 GND_50 50

GND

GND
+1.5V_S_G0L R39 0402

0ohms 1%
GND
0ohms 1%
GND

R43 0402
R44 0402

HW1 MM_DS_M2.5x0.45x2.5MM
HW6 M2.5X7MM

0ohms 1%
GND
0ohms 1%
GND

R45 0402
R46 0402

HW2 MM_DS_M2.5x0.45x2.5MM HW7 M2.5X7MM

+5.0V_S

+3.3V_S

+1.5V_S_G0L

R37 0402

4.7uF C22 10V 0402 10uF DNI C25 16V 0603

C23 0402

10uF DNI C24 16V 0603

R49 0402 R7 0402 R6 0402

4.7uF 10V

ICT1 ICT2
GND

0.1uF 50V

C34 0402

0ohms 1%
10Kohms 1%
10Kohms 1%

U5

1 IN_1 2 IN_2
GND

OUT_9 9 OUT_10 10

5 EN

FB 8 1V5_FB

3 PG

SS 7 1V5_SS

4 BIAS

GND 6

AP7173

THMPAD 11

560pF DNI C28 50V 0402

R38 0402

4.12Kohms 1%

GND
+1.5V_S Vout = 1.5V Iout = 0.4A DC tolerance = 2%

4.75Kohms 1%

GND

GND

GND

PICMG® COM-HPC® Carrier Design Guide

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Reference Schematics and Block Diagrams Figure 14: M.2 E-Key Site ­ WiFi Cards ­ PCIe Group 0 Low ­ PCIe Lane 2

+3.3V_S_G0L_M2_1

+3.3V_S_G0L_M2_1

GPIO

0402 R30

DNI

1% 10Kohms

0402 R29

DNI

1% 10Kohms

PCIe_CLK_SCL

PCIe_CLK_SDA

W_DISABLE#

0ohms 1%

DNI

R60 0402

PCI_RESET_G0L_2#

0ohms 1%

DNI

0ohms R57 1% 0402

DNI

M_2_EXP_DISABLE_2

R31

1% DNI 0402

10Kohms

GND

+3.3V_S_G0L_M2_1

74
72
70
NC
68
NC
66
NC
64
NC
62
R56 60 0402 58
56
54
52
50
NC
48
NC
46
NC
44
NC
42
NC
40
NC
38
NC
36
NC
34
NC
32
NC
30
NC
28
NC
26
NC
24
NC
22
NC
20
NC
18
16
NC
14
NC
12
NC
10
NC
8
NC
6
NC
4
2

J4
V_3V3_74 V_3V3_72 UIM_POWER_SRC/GPIO1/PEWAKE1# UIM_POWER_SNK/CLKREQ1# UIM_SWP/PERST1# RSVD_64 ALERT# I2C_CLK I2C_DATA W_DISABLE1# W_DISABLE2# PERST0# SUSCLK COEX1 COEX2 COEX3 VENDOR_DEFINED_42 VENDOR_DEFINED_40 VENDOR_DEFINED_38 UART_RTS UART_CTS UART_TXD CONNECTOR_KEY_30 CONNECTOR_KEY_28 CONNECTOR_KEY_26 CONNECTOR_KEY_24 UART_RXD UART_WAKE# GND_18 LED2# PCM_OUT/I2S_SD_OUT PCM_IN/I2S_SD_IN PCM_SYNC/I2S_WS PCM_CLK/I2S_SCK LED1# V_3V3_4 V_3V3_2

77 M_77

GND

TE-Connectivity_1-2199230

GND_75 RSVD/REFCLK1_N RSVD/REFCLK1_P
GND_69 RSVD/PER1_N RSVD/PER1_P
GND_63 RSVD/PET1_N RSVD/PET1_P
GND_57 PEWAKE0# CLKREQ0#
GND_51 REFCLK0_N REFCLK0_P
GND_45 PER0_N PER0_P GND_39 PET0_N PET0_P GND_33 CONNECTOR_KEY_31 CONNECTOR_KEY_29 CONNECTOR_KEY_27 CONNECTOR_KEY_25 SDIO_RESET# SDIO_WAKE# SDIO_DATA3 SDIO_DATA2 SDIO_DATA1 SDIO_DATA0 SDIO_CMD SDIO_CLK
GND_7 USB_DUSB_D+ GND_1

75
73 NC
71 NC
69
67 NC
65 NC
63
61 NC
59 NC
57
55
53
51
49
47
45
43
41
39
37
35
33
31 NC
29 NC
27 NC
25 NC
23 NC
21 NC
19 NC
17 NC
15 NC
13 NC
11 NC
9 NC
7
5
3
1

M_76 76

WAKE_G0L_2# PCIe_CLKREQ_G0L_2#

0ohms 1%

PCIe_CLK_G0L_2PCIe_CLK_G0L_2+

PCIe2_RXPCIe2_RX+

PCIe2_TXPCIe2_TX+

R61 0402

WAKE0#

USB5_CMC_USB5_CMC_+
GND

0805

2

3

1

4

L2 400mA 90R

USB5USB5+

COM COM COM COM
COM COM

Mounting hole for M.2 EXPANSION

MM_DS_M2.5x0.45x2.5MM DNI HW4

0402 R59

DNI

1% 0ohms
GND

ZNL1 Move solderpaste layer of HW5 to top side.

MM_DS_M2.5x0.45x2.5MM 0402

HW5

R58

1% 0ohms
GND

+3.3V_A +3.3V_S

0ohms 50mR
0ohms 50mR

R62 0805
DNI R63 0805

2.5 A

+3.3V_S_G0L_M2_1

C26 0603

C27 0603 0402 C35 0402 C36

10uF 16V 50V 0.1uF 50V 0.1uF

10uF 16V

GND

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Reference Schematics and Block Diagrams Figure 15: M.2 B-Key Site ­ Cell Modem Cards ­ PCIe Group 0 Low ­ PCIe Lane 3

+3.3V_S_3V7_3V3 J2

UIM_DETECT_G0L_BL
NC

WAKE0#

R53 0402

5 5

0ohms WAKE_G0L_2# 1%
PCIe_CLKREQ_G0L_3# PCI_RESET_G0L_3B# V_UIM_VCC_G0L_BU UIM_RST_G0L_BU UIM_CLK_G0L_BU UIM_DATA_G0L_BU UIM_DETECT_G0L_BU
NC

V_UIM_VCC_G0L_BL UIM_DATA_G0L_BL UIM_CLK_G0L_BL UIM_RST_G0L_BL

GPIO External Buff

G0L_M2_1_WIFI_DIS_2#

0402 R9

DNI

1% 10Kohms

GND

0402 R10

DNI

1% 10Kohms

GPIO GPIO

0402 R11

DNI

1% 10Kohms

0402 R13

DNI

1% 10Kohms

GND

G0L_M2_1_WIFI_DIS_1# MODEM_PWR_EN

0402 R12

DNI

1% 10Kohms

0402 R14

DNI

1% 10Kohms

74
72
70
68
NC
66
64
NC
62
NC
60
NC
58
NC
56
NC
54
52
50
48
46
44
42
40
38
NC
36
34
32
30
28
NC
26
24
NC
22
NC
20
NC
18
NC
16
NC
14
NC
12
NC
10
NC
8
6
4
2

V_3V3_74 V_3V3_72 V_3V3_70 SUSCLK SIM_DETECT COEX1 COEX2 COEX3 NC_58 NC_56 PEWAKE# CLKREQ# PERST# GPIO_4 GPIO_3 GPIO_2/ALERT# GPIO_1/SMB_DATA GPIO_0/SMB_CLK DEVSLP UIM_PWR UIM_DATA UIM_CLK UIM_RESET GPIO_8 GPIO_10 GPIO_7 GPIO_6 GPIO_5 CONNECTOR-KEY_18 CONNECTOR-KEY_16 CONNECTOR-KEY_14 CONNECTOR-KEY_12 GPIO_9/DAS/DSS#/LED1# W_DISABLE#1 FULL_CARD_POWER_OFF# V_3V3_4 V_3V3_2

77 M_77

GND

TE-Connectivity_1-2199230_CARD

CONFIG_2 GND_73 GND_71
CONFIG_1 RESET#
ANTCTL3 ANTCTL2 ANTCTL1 ANTCTL0
GND_57 REFCLKP REFCLKN
GND_51 PETP0/SATA_A+ PETN0/SATA_A-
GND_45 PERP0/SATA_BPERN0/SATA_B+
GND_39 PETP1/USB3_TX+/SSIC_TxP PETN1/USB3_TX-/SSIC-TxN
GND_33 PERP1/USB3_RX+/SSIC_RXP PERN1/USB3_RX-/SSIC_RXN
GND_27 DPR
GPIO_11 CONFIG_0 CONNECTOR-KEY_19 CONNECTOR-KEY_17 CONNECTOR-KEY_15 CONNECTOR-KEY_13
GND_11 USB_DUSB_D+ GND_5 GND_3 CONFIG_3
M_76

75 NC
73
71
69 NC
67
65 NC
63 NC
61
59 NC
57
55
53
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23 NC
21 NC
19 NC
17 NC
15 NC
13 NC
11
9
7
5
3
1 NC
76

PCI_RESET_G0L_3A#
MOD1_V_3V7_3V3_SEL_G0L *3.7 or 3.3 voltage select pin not shown
PCIe_CLK_G0L_3+ PCIe_CLK_G0L_3PCIe3_TX+ PCIe3_TXPCIe3_RX+ PCIe3_RXUSB0_SSTX0+ USB0_SSTX0USB0_SSRX0+ USB0_SSRX0M2_DPR_G0L_B
USB0USB0+

0402

GND

10Kohms DNI R8

1%

Pinout based on using a

+3.3V_S_3V7_3V3

Sierra Wireless EM7455

GND

5
5 5 COM COM COM COM COM COM COM COM
COM COM

C12 1210 C13 1210 C14 0402 C1 0402 C18 0402 C21 0402 C19 0402 C20 0402

100uF 10V
100uF 10V 1uF 16V
0.1uF 25V
0.01uF 16V
0.001uF 16V 33pF 50V 10pF 50V

0402 C4

VCC_G0L_T3

U8 5 V_VCC

2 GND SRV05-4

IO1 1

IO2 3

IO3 4

IO4

6 NC

25V 0.1uF

GND

GND
UIM_DATA_G0L_BU UIM_CLK_G0L_BU

UIM_RST_G0L_BU

UIM_DATA_G0L_BL UIM_CLK_G0L_BL
UIM_RST_G0L_BL U7
VCC_G0L_T2 5 V_VCC

GND

GND

2 GND
1045-5110 SRV05-4

IO1 1

IO2 3

IO3 4

IO4

6 NC

0402 C3

25V 0.1uF

GND
M.2 Retention Hardware
HW3
GND
M2.5x2.5MM

Dual SIM card socket

7-U IO_7-U 3-U CLK_3-U

J1 UPPER CARD

V_VCC_1-U 1-U V_VPP_6-U 6-U

2-U RST_2-U 5-U GND_5-U

RSVD_4-U 4-U NC RSVD_8-U 8-U NC

7-L IO_7-L 3-L CLK_3-L

LOWER CARD

2-L RST_2-L

5-L GND_5-L

S1 S1 S3 S3

GND
CH_GND

GRADCONN_CH03-AN080-0BR

V_VCC_1-L 1-L V_VPP_6-L 6-L

RSVD_4-L 4-L

NC

RSVD_8-L 8-L

NC

S2 S2 S4 S4
CH_GND

V_UIM_VCC_G0L_BU V_UIM_VPP_G0L_BU

0ohms 1%

DNI

R51 0402

V_UIM_VCC_G0L_BL V_UIM_VPP_G0L_BL

0ohms 1%

DNI

R52 0402

1 IO1 3 IO2 4 IO3 6 IO4

U6 V_VCC 5
GND 2

SRV05-4

VCC_G0L_T1

GND

GND

C2 0402

0.1uF 25V

PICMG® COM-HPC® Carrier Design Guide

Rev. 2.1 / Aug 10, 2023 40/159

Reference Schematics and Block Diagrams Figure 16: Clock and Reset Buffers for PCIe Group 0 Low Example Circuits

+3.3V_S

+3.3V_S_VDD

600

FB1

2A

0805

+3.3V_S_VDD
600 1A

FB3 0603

+3.3V_S_VDDR

+3.3V_S_VDD
600 1A

FB2 0603

+3.3V_S_VDDA

C39 0603 C8 0402

1uF C17 16V 0402

C38 0603 C7 0402

1uF C16 16V 0402

C37 0603 C5 0402 C6 0402

C15 0402 C40 0603

10uF 10V 0.1uF 25V

10uF 10V 0.1uF 25V

10uF 10V 0.1uF 25V 0.1uF 25V

1uF 16V 10uF 10V

GND

PCIe_CLKREQ_G0L_1# PCIe_CLKREQ_G0L_2# PCIe_CLKREQ_G0L_3#

COM COM

PCIe_REFCLK0_LO+ PCIe_REFCLK0_LO-

COM PCIe_CLKREQ0_LO#

GND

GND

GND

BW_MODE_G0L PWRGD_PD_G0L# SADR_G0L

U1 1 HIBW_BYPM_LOBW# 31 CK_PWRGD_PD# 32 SADR

PCIe_CLK_SDA PCIe_CLK_SCL

0ohms 1%

DNI

0402

0ohms 1%

DNI

0402

PCIe_CLKREQ_G0L_0#

10 SDATA_3V3 9 SCLK_3V3
12 OE0# 19 OE1# 24 OE2# 29 OE3#

5 CLK_IN+ 6 CLK_IN-

V_3V3_DIG V_3V3_VDDR V_3V3_VDDA

GND

GND

+3.3V_S

+3.3V_S_VDDR

11

+3.3V_S_VDDA

4

+3.3V_S_VDD

21

V_3V3_VDDO_15 15 V_3V3_VDDO_25 25

DIF0+ 13 DIF0- 14 DIF1+ 17 DIF1- 18 DIF2+ 22 DIF2- 23 DIF3+ 27 DIF3- 28

PCIe_CLK_G0L_0+ PCIe_CLK_G0L_0-
PCIe_CLK_G0L_1+ PCIe_CLK_G0L_1-
PCIe_CLK_G0L_2+ PCIe_CLK_G0L_2-
PCIe_CLK_G0L_3+ PCIe_CLK_G0L_3-

NC 2 FB_DNC+ NC 3 FB_DNC-
8 GND_DIG 33 GND_TAB

NC_7 NC_16 NC_20 NC_26 NC_30

7 NC
16 NC
20 NC
26 NC
30 NC

GND

9DBL0452

0ohms

R54 0402
GND

COM-HPD external PCIe Clock always requested due to i210 chip down

+3.3V_S_VDD

R25 0402

0402

10Kohms DNI R27

R23 0402

R21 0402

R19 0402

R17 0402

R15 0402

DNI

10Kohms 1%

1%

10Kohms 1%

10Kohms 1%

10Kohms 1%

10Kohms 1%

10Kohms 1%

PCIe_CLKREQ_G0L_3# PCIe_CLKREQ_G0L_2# PCIe_CLKREQ_G0L_1# PCIe_CLKREQ_G0L_0# SADR_G0L PWRGD_PD_G0L# BW_MODE_G0L
+3.3V_S

0402

0402

0402

R22 0402

0402

R28 0402

0402

SADR: SMBUS ADDR
0 0x6B (7-bit) M 0x6C (7-bit) 1 0x6D (7-bit) (Default)
BW_MODE
0 LOW BW MODE M BYPASS MODE (Default) 1 HIGH BW MODE

10Kohms DNI R26

10Kohms DNI R24

10Kohms DNI R20

10Kohms DNI R18

10Kohms DNI R16

1%

10Kohms 1%

1%

10Kohms 1%

1%

1%

1%

R1 0402 R2 0402 C10 0402

PCIe_CLK_SCL PCIe_CLK_SDA

2.8Kohms 1%
2.8Kohms 1% 0.1uF 25V

GND

U2

8 V_VCCB

V_VCCA

+3.3V_S

1

*Only on buffer per board needed

7 B0 6 B1

A0 2 A1 3

SMB_CLK SMB_DAT

COM COM

4 GND

OE 5

GND

FXMA2102

COM

PLTRST#

U3

1

VCC 5

+3.3V_S

2

1

4

GND

GND 3

0.1uF 25V

C9 0402

74LVC1G125

GND

22ohms 1%
22ohms 1%
22ohms 1%

R34 0402
R32 0402
R33 0402

PCI_RESET_G0L_0# PCI_RESET_G0L_1# PCI_RESET_G0L_2#

U4

1

VCC 5

+3.3V_S

2

1

4

GND

GND 3

0.1uF 25V

C11 0402

74LVC1G125

GND

22ohms 1%
22ohms 1%

R35 0402
R36 0402

PCI_RESET_G0L_3A# PCI_RESET_G0L_3B#

*Max 4 outputs per buffer *Push/Pull design use LVC07 wih PU resistor for OC designs

PICMG® COM-HPC® Carrier Design Guide

Rev. 2.1 / Aug 10, 2023 41/159

Reference Schematics and Block Diagrams

3.6.4.

Dual PCIe x4 M.2 M Key NVME SSDs Examples on PCIe Group 0 High

The following three figures illustrate a dual PCIe x4 M.2 M Key deployment for NVME SSDs. The COM-HPC specification recommends that PCIe Group 0 High be used for this purpose.

Figure 17: M.2 M-Key Site for NVME SSD Card #1 in Group 0 High PCIe Lanes 8:11

22x80mm M-type

+3.3V_S

4.2mm connector height

C28 0805 C29 0805 C22 0603 C7 0402 C8 0402 C9 0402 C10 0402 C11 0402 C12 0402

22uF 6.3V 22uF 6.3V 10uF 10V 0.1uF 25V 0.1uF 25V 0.1uF 25V 0.1uF 25V 0.1uF 25V 0.1uF 25V

J2

REV 1.1

G0H_M2_1_SUSCLK

R8 0402
R9

10Kohms 1%
10Kohms

GND GND GND GND GND GND GND GND GND

PCIe_CLKREQ_G0H_1# PCI_RESET_G0H_1#
Not connecting SMBus on connectors to COM-HPD main SMBus due to the inability to garantee unique SMBus addresses

0ohms 1%

GND
G0H_1_PEWAKE#
R32 G0H_1_PERST# 0402

SMB_DAT_G0H_1 SMB_CLK_G0H_1 M2_G0H_1_DEVSLP

R10 0402

10Kohms

10Kohms

1%

1%

R13

R12

+1.8V_S_G0H

GND

M2_G0H_1_SSD_ACT#

10Kohms 1%

1.5Kohms 1%

R27 0402

+3.3V_S

R25 0402

74
72
70
68
66
NC
64
NC
62
NC
60
NC
58
NC
56
NC
54
52
50
48
NC
46
NC
44
NC
42
40
38
36
NC
34
NC
32
NC
30
NC
28
NC
26
NC
24
NC
22
NC
20
NC
18
16
14
12
10
8
NC
6
NC
4
2

V_3V3_74 V_3V3_72 V_3V3_70 SUSCLK CONNECTOR_KEY_66 CONNECTOR_KEY_64 CONNECTOR_KEY_62 CONNECTOR_KEY_60 NC_58 NC_56 PEWAKE# CLKREQ# PERST# NC_48 NC_46 ALERT# SMB_DATA SMB_CLK DEVSLP NC_36 NC_34 NC_32 NC_30 NC_28 NC_26 NC_24 NC_22 NC_20 V_3V3_18 V_3V3_16 V_3V3_14 V_3V3_12 DAS/DSS/LED1# NC_8 NC_6 V_3V3_4 V_3V3_2

77 MTG_77

GND

TE-Connectivity_1-2199230_CARD

2.21Kohms 1%

GND

GND_75 GND_73 GND_71
PEDET NC_67 CONNECTOR_KEY_65 CONNECTOR_KEY_63 CONNECTOR_KEY_61 CONNECTOR_KEY_59 GND_57 REFCLK+ REFCLKGND_51 PET0+/SATA-A+ PET0-/SATA-AGND_45 PER0+/SATA-BPER0-/SATA-B+ GND_39 PET1+ PET1GND_33 PER1+ PER1GND_27 PET2+ PET2GND_21 PER2+ PER2GND_15 PET3+ PET3GND_9 PER3+ PER3GND_3 GND_1 MTG_76

75 73 71 69
NC
67 NC
65 NC
63 NC
61 NC
59 NC
57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 76

GND

Stagered spin-up isn't disabled by default. From SATA specification, DAS pullup voltage is Vhh = 1.8V to 2.1V max. It must be buffered to drive a LED.

M.2 Retention Hardware
HW2
GND
M2.5x2.5MM

PCIe_CLK_G0H_1+ PCIe_CLK_G0H_1-
PCIe8_TX+ PCIe8_TX-
PCIe8_RX+ PCIe8_RX-
PCIe9_TX+ PCIe9_TX-
PCIe9_RX+ PCIe9_RX-
PCIe10_TX+ PCIe10_TX-
PCIe10_RX+ PCIe10_RX-
PCIe11_TX+ PCIe11_TX-
PCIe11_RX+ PCIe11_RX-

COM COM
COM COM
COM COM
COM COM
COM COM
COM COM
COM COM
COM COM

+3.3V_S

270ohms

R31 0402

M2_G0H_1_SSD_ACT_D#

R11 0402

Y D2

90 to 180mcd @ 20mA, 25C 22 to 45mcd @ 6mA, 25C Vf @ 20mA = 1.9V min; 2.0V typ; 2.4V max Vf @ 6mA = 1.85V typ.

M2_G0H_1_SSD_ACT#

1

3 Q3 MMBT3904 SOT23
2

GND

10Kohms 1%

M2_G0H_1_SSD_ACT_Q#

M2_G0H_1_SSD_ACT

3

Q4

1

MMBT3904

SOT23

2

GND

+3.3V_S

R33 0402

+3.3V_S

+3.3V_S

R38 0402

4.02Kohms 1%

V_1V8_PGOOD

C34 0805

C35 0805

10uF 10V

10uF 10V

GND

GND

1uF C33 10V 0402

0ohms

1 IN_1 2 IN_2 5 EN 3 PG 4 BIAS
AP7173
GND

@0.58A max

U2 OUT_9 9
OUT_10 10 FB 8 SS 7
GND 6 THMPAD 11

1V8_FB 1V8_SS

C32 0402
R1 0402

1.24Kohms 1%

R37 0402

VOUT = 0.8*(1+R1/R2) 1.792V (typ)

0.001uF 50V
1Kohms 0.1%

GND

GND

GND

22uF 6.3V

C30 0805

+1.8V_S_G0H
GND

PICMG® COM-HPC® Carrier Design Guide

Rev. 2.1 / Aug 10, 2023 42/159

Reference Schematics and Block Diagrams Figure 18: M.2 M -Key Site for NVME SSD #2 in Group 0 PCIe Lanes 12:15

22x80mm M-type

+3.3V_S

4.2mm connector height

C26 0805 C27 0805 C21 0603 C1 0402 C2 0402 C3 0402 C4 0402 C5 0402 C6 0402

22uF 6.3V 22uF 6.3V 10uF 10V 0.1uF 25V 0.1uF 25V 0.1uF 25V 0.1uF 25V 0.1uF 25V 0.1uF 25V

G0H_M2_2_SUSCLK

74 V_3V3_74

J1

R2 0402 R3 0402

72 V_3V3_72

70 V_3V3_70

68 SUSCLK

66
NC

CONNECTOR_KEY_66

10Kohms 1%
10Kohms

64
NC

CONNECTOR_KEY_64

GND GND GND GND GND GND GND GND GND

62
NC

CONNECTOR_KEY_62

60
NC

CONNECTOR_KEY_60

GND

58
NC

NC_58

56
NC

NC_56

G0H_2_PEWAKE#

54 PEWAKE#

PCIe_CLKREQ_G0H_2#

52 CLKREQ#

PCI_RESET_2#

50 PERST#

48
NC

NC_48

Not connecting SMBus on connectors

46
NC

NC_46

to COM-HPD main SMBus due to the inability to garantee unique SMBus addresses

SMB_DAT_G0H_2 SMB_CLK_G0H_2

44
NC
42
40

ALERT# SMB_DATA SMB_CLK

REV 1.1

R4 0402

10Kohms

10Kohms

M2_G0H_1_DEVSLP

38 DEVSLP

36
NC

NC_36

1%

1%

34
NC

NC_34

32
NC

NC_32

30
NC

NC_30

+3.3V_S

28
NC

NC_28

R26 0402

10Kohms 1%

R6

R7

26
NC

NC_26

24
NC

NC_24

22
NC

NC_22

+1.8V_S_G0H

GND

20
NC

NC_20

18 V_3V3_18

1.5Kohms 1%

16 V_3V3_16

14 V_3V3_14

12 V_3V3_12

M2_G0H_2_SSD_ACT#

10 DAS/DSS/LED1#

R24 0402

NC 8 NC_8

NC 6 NC_6

4 V_3V3_4

2 V_3V3_2

77 MTG_77

GND

TE-Connectivity_1-2199230_CARD

2.21Kohms 1%

GND

GND_75 GND_73 GND_71
PEDET NC_67 CONNECTOR_KEY_65 CONNECTOR_KEY_63 CONNECTOR_KEY_61 CONNECTOR_KEY_59 GND_57 REFCLK+ REFCLKGND_51 PET0+/SATA-A+ PET0-/SATA-AGND_45 PER0+/SATA-BPER0-/SATA-B+ GND_39 PET1+ PET1GND_33 PER1+ PER1GND_27 PET2+ PET2GND_21 PER2+ PER2GND_15 PET3+ PET3GND_9 PER3+ PER3GND_3 GND_1 MTG_76

75 73 71 69
NC
67 NC
65 NC
63 NC
61 NC
59 NC
57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 76

GND

Stagered spin-up isn't disabled by default. From SATA specification, DAS pullup voltage is Vhh = 1.8V to 2.1V max. It must be buffered to drive a LED.

M.2 Retention Hardware
HW1
GND
M2.5x2.5MM

PCIe_CLK_G0H_2+ PCIe_CLK_G0H_2-
PCIe12_TX+ PCIe12_TX-
PCIe12_RX+ PCIe12_RX-
PCIe13_TX+ PCIe13_TX-
PCIe13_RX+ PCIe13_RX-
PCIe14_TX+ PCIe14_TX-
PCIe14_RX+ PCIe14_RX-
PCIe15_TX+ PCIe15_TX-
PCIe15_RX+ PCIe15_RX-

COM COM
COM COM
COM COM
COM COM
COM COM
COM COM
COM COM
COM COM

SSD Activity LED

270ohms

R30 M2_G0H_2_SSD_ACT_D# 0402

+3.3V_S

R5 0402

Y D1

90 to 180mcd @ 20mA, 25C 22 to 45mcd @ 6mA, 25C Vf @ 20mA = 1.9V min; 2.0V typ; 2.4V max Vf @ 6mA = 1.85V typ.

M2_G0H_2_SSD_ACT#

1

3 Q1 MMBT3904 SOT23
2

GND

10Kohms 1%

M2_G0H_2_SSD_ACT_Q#

3

M2_G0H_2_SSD_ACT

1

Q2 MMBT3904 SOT23

2

GND

The M.2 M-Key connector used must have a PCIe "speed rating" at least as high as the link speed being used (PCIe Gen 3, 4 or 5).

PCIe Gen 3 capable M.2 connectors are common. At the time of this writing, PCIe Gen 4 and 5 capable M.2 connectors are not common. PCIe Gen 4 capable M.2 connectors are available from Amphenol FCI.

PICMG® COM-HPC® Carrier Design Guide

Rev. 2.1 / Aug 10, 2023 43/159

Reference Schematics and Block Diagrams Figure 19: Clock Buffer and Reset for PCIe Dual M.2 NVME SSD PCIe Group 0 High

+3.3V_S_G0H_VDD

+3.3V_S_G0H_VDD

R40 0402 R39 0402

0402 R22 0402 R20 0402 R18 0402 R16 0402 R14

1% 10Kohms
1% 10Kohms
1% 10Kohms
1% 10Kohms
1% 10Kohms

BW_MODE_G0H PWRGD_PD_G0H# SADR_G0H PCIe_CLKREQ_G0H_1# PCIe_CLKREQ_G0H_2#

1Kohms 1%
1Kohms 1%

SADR: SMBUS ADDR
0 0x6B (7-bit) M 0x6C (7-bit) 1 0x6D (7-bit) (Default)
BW_MODE
0 LOW BW MODE M BYPASS MODE (DEFAULT) 1 HIGH BW MODE

+3.3V_S_G0H_VDDA

0402 R15

0402 R17

0402 R19

0402 R21

0402 R23

COM COM
COM COM COM

DNI

DNI

DNI

DNI

1% 10Kohms

1% 10Kohms

1% 10Kohms

SMB_DAT SMB_CLK
PCIe_CLKREQ_G0H_1# PCIe_CLKREQ_G0H_2#

GND

0ohms 1%

DNI

R41 0603

0ohms 1%

DNI

R42 0603

1% 10Kohms

1% 10Kohms

BW_MODE_G0H PWRGD_PD_G0H# SADR_G0H

U4 24 HIBW_BYPM_LOBW# 22 CK_PWRGD_PD# 23 SADR

CLK_BUFF_SMB_DATA CLK_BUFF_SMB_CLK

7 SDATA_3V3 9 SCLK_3V3 15 OE0# 19 OE1#

PCIe_REFCLK0_HI+ PCIe_REFCLK0_HIPCIe_CLKREQ0_HI#

+3.3V_S 5

+3.3V_S

4

0.1uF 25V

C20

3

0402

GND

VCC GND

0ohms

DNI

R34 0402

GND

U1

1

2

74LVC1G08

4 CLK_IN+ 5 CLK_IN-
NC 1 FB_DNC+ NC 2 FB_DNC-
6 GND_DIG 25 GND_PAD
9DBL0252
GND

+3.3V_S_G0H_VDDR +3.3V_S_G0H_VDD
V_3V3_DIG 8 V_3V3_VDDR 3 V_3V3_VDDA 16 V_3V3_VDDO_21 21 V_3V3_VDDO_10 10

DIF0+ 13 DIF0- 14 DIF1+ 17 DIF1- 18

PCIe_CLK_G0H_1+ PCIe_CLK_G0H_1-
PCIe_CLK_G0H_2+ PCIe_CLK_G0H_2-

NC_11 NC_12 NC_20

11 NC
12 NC
20 NC

+3.3V_S

+3.3V_S_G0H_VDD

+3.3V_S_VDD

+3.3V_S_G0H_VDDR

+3.3V_S_VDD

+3.3V_S_G0H_VDDA

80

FB1

4A

1206

0ohms 1%

R35 0402

0ohms 1%

R36 0402

C25 0603 C18 0402

C24 0603 C17 0402

C31 0805 C23 0603 C13 0402 C14 0402 C15 0402 C16 0402

10uF 10V
0.1uF 25V

10uF 10V
0.1uF 25V

22uF 6.3V 10uF 10V 0.1uF 25V 0.1uF 25V 0.1uF 25V 0.1uF 25V

GND
COM PLTRST#

GND

GND

U3

1

VCC 5

+3.3V_S

2

1

4 PCI_RESET#

GND

GND 3

0.1uF 25V

C19 0402

74LVC1G125

GND

22ohms 1%
22ohms 1%

R28 0402
R29 0402

G0H_PCI_RESET_1# G0H_PCI_RESET_2#

A dual channel clock buffer is used as there are two PCIe x4 links implemented in this PCIe Group 0 High example. The COM-HPC PCIe_CLKREQ0_HI# signal is driven by logic gate U1 in the Figure just above, resulting in a clock request if either one or both of the NVMe cards are present. Alternatively, U1 could be removed and the COM-HPC Group 0 High clock request line held low by R34, in which case the Group 0 High PCIe clock pair would always run.
The clock buffer shown is the 9DBL0252 from Renesas / IDT. It is PCIe Gen 1,2,3,4 and 5 capable.
The PLTRST# buffer shown, U3, is a 74LVC1G125 device that tolerates a signal input between 0 and 5.5V even in the absence of the VCC to the device. The PLTRST# signal is in the S5 power domain; the VCC applied to U3 is in the S0 domain.

PICMG® COM-HPC® Carrier Design Guide

Rev. 2.1 / Aug 10, 2023 44/159

Reference Schematics and Block Diagrams

3.6.5.

PCIe x16 Slot Card Site on PCIe Group 1

Figure 20: PCIe x16 Slot Card Site on PCIe Group 1 PCIe Lanes 16:31

ICT1 ICT2 ICT3 ICT4 ICT5

J1 A5 JTAG2_TCK A6 JTAG3_TDI A7 JTAG4_TDO A8 JTAG5_TMS B9 JTAG1_TRST#

COM COM

PCIe_REFCLK1+ PCIe_REFCLK1-

A13 REFCLK+ A14 REFCLK-

SECTION 1 OF 2

COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM

PCIe16_TX+ PCIe16_TXPCIe17_TX+ PCIe17_TXPCIe18_TX+ PCIe18_TXPCIe19_TX+ PCIe19_TXPCIe20_TX+ PCIe20_TXPCIe21_TX+ PCIe21_TXPCIe22_TX+ PCIe22_TXPCIe23_TX+ PCIe23_TXPCIe24_TX+ PCIe24_TXPCIe25_TX+ PCIe25_TXPCIe26_TX+ PCIe26_TXPCIe27_TX+ PCIe27_TXPCIe28_TX+ PCIe28_TXPCIe29_TX+ PCIe29_TXPCIe30_TX+ PCIe30_TXPCIe31_TX+ PCIe31_TX-

B14 PET0+ B15 PET0B19 PET1+ B20 PET1B23 PET2+ B24 PET2B27 PET3+ B28 PET3B33 PET4+ B34 PET4B37 PET5+ B38 PET5B41 PET6+ B42 PET6B45 PET7+ B46 PET7B50 PET8+ B51 PET8B54 PET9+ B55 PET9B58 PET10+ B59 PET10B62 PET11+ B63 PET11B66 PET12+ B67 PET12B70 PET13+ B71 PET13B74 PET14+ B75 PET14B78 PET15+ B79 PET15-

COM

WAKE0# 0ohms 1%

R5

B11

0402

COM

SMB_CLK 0ohms 1%

DNI

R6 0402

B5

COM

SMB_DAT 0ohms 1%

DNI

R7 0402

B6

A19

Not connecting SMBus on connectors NC A32

to COM-HPD main SMBus due to the inability to garantee unique SMBus

NC NC

A33

addresses

A50
NC

B12
NC

EPRBRK_G1_1#

B30

B82
NC

WAKE#
SMCLK SMDAT
RSVD_A19 RSVD_A32 RSVD_A33 RSVD_A50 RSVD_B12 RSVD_B30 RSVD_B82

FCI_10141523-123A

SECTION 2 OF 2

J1 A4 GND_A4 A12 GND_A12 A15 GND_A15 A18 GND_A18 A20 GND_A20 A23 GND_A23 A24 GND_A24 A27 GND_A27 A28 GND_A28 A31 GND_A31 A34 GND_A34 A37 GND_A37 A38 GND_A38 A41 GND_A41 A42 GND_A42 A45 GND_A45 A46 GND_A46 A49 GND_A49 A51 GND_A51 A54 GND_A54 A55 GND_A55 A58 GND_A58 A59 GND_A59 A62 GND_A62 A63 GND_A63 A66 GND_A66 A67 GND_A67 A70 GND_A70 A71 GND_A71 A74 GND_A74 A75 GND_A75 A78 GND_A78 A79 GND_A79 A82 GND_A82

M1 M1

GND

FCI_10141523-123A

+12V_S

+3.3V_S

+3.3V_A

V_12V0_A2 A2 V_12V0_A3 A3
V_3V3_A9 A9 V_3V3_A10 A10 V_12V0_B1 B1 V_12V0_B2 B2 V_12V0_B3 B3
V_3V3_B8 B8 V_3V3_AUX B10

PERST# A11 PER0+ A16 PER0- A17 PER1+ A21 PER1- A22 PER2+ A25 PER2- A26 PER3+ A29 PER3- A30 PER4+ A35 PER4- A36 PER5+ A39 PER5- A40 PER6+ A43 PER6- A44 PER7+ A47 PER7- A48 PER8+ A52 PER8- A53 PER9+ A56 PER9- A57
PER10+ A60 PER10- A61 PER11+ A64 PER11- A65 PER12+ A68 PER12- A69 PER13+ A72 PER13- A73 PER14+ A76 PER14- A77 PER15+ A80 PER15- A81

PCI_RESET_G1_1# PCIe16_RX+ PCIe16_RXPCIe17_RX+ PCIe17_RXPCIe18_RX+ PCIe18_RXPCIe19_RX+ PCIe19_RXPCIe20_RX+ PCIe20_RXPCIe21_RX+ PCIe21_RXPCIe22_RX+ PCIe22_RXPCIe23_RX+ PCIe23_RXPCIe24_RX+ PCIe24_RXPCIe25_RX+ PCIe25_RXPCIe26_RX+ PCIe26_RXPCIe27_RX+ PCIe27_RXPCIe28_RX+ PCIe28_RXPCIe29_RX+ PCIe29_RXPCIe30_RX+ PCIe30_RXPCIe31_RX+ PCIe31_RX-

COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM

PRSNT1# A1 PRSNT2#_B17 B17 PRSNT2#_B31 B31 PRSNT2#_B48 B48 PRSNT2#_B81 B81

GND
PCIe_CLKREQ_G1_1#

Signal can also be used as a present

1% DNI 0402

+3.3V_S

10Kohms

R4

COM

GND_B4 B4 GND_B7 B7 GND_B13 B13 GND_B16 B16 GND_B18 B18 GND_B21 B21 GND_B22 B22 GND_B25 B25 GND_B26 B26 GND_B29 B29 GND_B32 B32 GND_B35 B35 GND_B36 B36 GND_B39 B39 GND_B40 B40 GND_B43 B43 GND_B44 B44 GND_B47 B47 GND_B49 B49 GND_B52 B52 GND_B53 B53 GND_B56 B56 GND_B57 B57 GND_B60 B60 GND_B61 B61 GND_B64 B64 GND_B65 B65 GND_B68 B68 GND_B69 B69 GND_B72 B72 GND_B73 B73 GND_B76 B76 GND_B77 B77 GND_B80 B80
M2 M2
GND

+12V_S

+3.3V_S

+3.3V_A

C7 0603

C5 1210 C6 1210

C3 7343-31 C4 7343-31

10uF 16V X6S

100uF 10V X6S
100uF 10V X6S

100uF 25V PTA
100uF 25V PTA

GND

GND

GND

GND

GND

+3.3V_S

+3.3V_S

0402 R3

0402 R2 0402 C2

EPRBRK_G1_1# Open Drain Signal
GND

1% 10Kohms
25V 0.1uF

Optional

1% 10Kohms

U1 5 VCC
4

NC 1 NC 2

3 GND

74LVC1G07

GPIO_EPRBRK_G1_1#

+3.3V_S

U2

5 VCC

1

PCI_RESET_G1_1#

R1 0402

22ohms 4 1%

1

2

PLTRST# COM

C1 0402

0.1uF 25V

3 GND

GND

GND

74LVC1G125

No PCIe clock buffer is needed as there is only one PCIe link in this example. The COM-HPC Group 1 PCIe clock pair is used directly. If the group is split into two or more links, then a PCIe clock buffer would be required.

The slot connector used must be rated and qualified for the PCIe link speed expected. Slot connectors rated for PCIe Gen 3 and below are common. Connectors rated for PCIe Gen 4 and Gen 5 are at the time of this writing are still new. Such parts are available from Amphenol FCI and others.

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Reference Schematics and Block Diagrams

3.6.6.

PCIe Group 2

Figures 21 through 24 below illustrate the implementation of 3 PCIe slots on COM-HPC PCIe Group 2, along with a PCIe clock buffer appropriate for use with PCIe Gen 4 and below. The slot RESET# signals come from a buffer in Figure 24. Additional notes are provided after the last Figure in this series.
Figure 21: PCIe x8 Slot Card Site on PCIe Group 2 PCIe Lanes 32:39

ICT11 ICT12 ICT13 ICT14 ICT15

J1 A5 JTAG2_TCK A6 JTAG3_TDI A7 JTAG4_TDO A8 JTAG5_TMS B9 JTAG1_TRST#

PCIe_CLK_G2_1+ PCIe_CLK_G2_1-

A13 REFCLK+ A14 REFCLK-

COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM

PCIe32_TX+ PCIe32_TXPCIe33_TX+ PCIe33_TXPCIe34_TX+ PCIe34_TXPCIe35_TX+ PCIe35_TXPCIe36_TX+ PCIe36_TXPCIe37_TX+ PCIe37_TXPCIe38_TX+ PCIe38_TXPCIe39_TX+ PCIe39_TX-

B14 PET0+ B15 PET0B19 PET1+ B20 PET1B23 PET2+ B24 PET2B27 PET3+ B28 PET3B33 PET4+ B34 PET4B37 PET5+ B38 PET5B41 PET6+ B42 PET6B45 PET7+ B46 PET7-

COM

WAKE0# R28 0402

0ohms WAKE0_G2_3# 1%

B11 WAKE#

PCIe_CLK_SCL

R33 0402

DNI

0ohms 1%

B5 SMCLK

PCIe_CLK_DAT

R34 0402

DNI

0ohms 1%

B6 SMDAT

Not connecting SMBus on connectors

NC A19 RSVD_A19

to COM-HPD main SMBus due to the inability to garantee unique SMBus addresses

NC A32 RSVD_A32 NC A33 RSVD_A33 NC B12 RSVD_B12

EPRBRK_G2_1#

B30 RSVD_B30

A4 GND_A4 A12 GND_A12 A15 GND_A15 A18 GND_A18 A20 GND_A20 A23 GND_A23 A24 GND_A24 A27 GND_A27 A28 GND_A28 A31 GND_A31 A34 GND_A34 A37 GND_A37 A38 GND_A38 A41 GND_A41 A42 GND_A42 A45 GND_A45 A46 GND_A46 A49 GND_A49

M1 M1

GND

FCI_10141523-122Y

+12V_S V_12V0_A2 A2 V_12V0_A3 A3
V_3V3_A9 A9 V_3V3_A10 A10 V_12V0_B1 B1 V_12V0_B2 B2 V_12V0_B3 B3
V_3V3_B8 B8 V_3V3_AUX B10

+3.3V_S

+3.3V_A

PERST# A11 PER0+ A16 PER0- A17 PER1+ A21 PER1- A22 PER2+ A25 PER2- A26 PER3+ A29 PER3- A30 PER4+ A35 PER4- A36 PER5+ A39 PER5- A40 PER6+ A43 PER6- A44 PER7+ A47 PER7- A48

PCI_RESET_G2_1# PCIe32_RX+ PCIe32_RXPCIe33_RX+ PCIe33_RXPCIe34_RX+ PCIe34_RXPCIe35_RX+ PCIe35_RXPCIe36_RX+ PCIe36_RXPCIe37_RX+ PCIe37_RXPCIe38_RX+ PCIe38_RXPCIe39_RX+ PCIe39_RX-

COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM

PRSNT1# A1 PRSNT2#_B17 B17 PRSNT2#_B31 B31 PRSNT2#_B48 B48
GND_B4 B4 GND_B7 B7 GND_B13 B13 GND_B16 B16 GND_B18 B18 GND_B21 B21 GND_B22 B22 GND_B25 B25 GND_B26 B26 GND_B29 B29 GND_B32 B32 GND_B35 B35 GND_B36 B36 GND_B39 B39 GND_B40 B40 GND_B43 B43 GND_B44 B44 GND_B47 B47 GND_B49 B49
M2 M2

GND
PCIe_CLKREQ_G2_1#
Signal can also be used as a present

+12V_S

+3.3V_S

+3.3V_A

C11 0603

C6 1210

C3 7343-31

100uF 10V X6S

100uF 25V PTA

GND

GND

GND

GND

+3.3V_S

+3.3V_S

10uF 16V X6S

COM

0402 R17

0402 R16 0402 C14

1% 10Kohms

EPRBRK_G2_1#

Open Drain Signal

1% 10Kohms
25V 0.1uF

Optional

U5 5 VCC
4

NC 1 NC 2 GPIO_EPRBRK__G2_1#

3 GND

Driven from any source os GPIO logic

GND

74LVC1G07

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Reference Schematics and Block Diagrams Figure 22: PCIe x4 Slot Card Site on PCIe Group 2 PCIe Lanes 40:43

+12V_S

+3.3V_S

+3.3V_S

+3.3V_A

C1 7343-31 C4 1210 C9 0603

100uF 25V PTA
100uF 10V X6S 10uF 16V X6S

GND

GND

GND

ICT2 ICT3 ICT4 ICT5

PCI_RESET_G2_2#

COM COM
COM COM

PCIe_CLK_G2_2+ PCIe_CLK_G2_2-
PCIe40_RX+ PCIe40_RX-

COM COM

PCIe41_RX+ PCIe41_RX-

COM COM

PCIe42_RX+ PCIe42_RX-

COM COM

PCIe43_RX+ PCIe43_RX-

+12V_S

A1 PRSNT1#

A2 V_12V0_A2

GND

A3 V_12V0_A3

A4 GND_A4

A5 JTAG2_TCK

A6 JTAG3_TDI

A7 JTAG4_TDO

A8 JTAG5_TMS

A9 V_3V3_A9

A10 V_3V3_A10

A11 PERST#

J2
V_12V0_B1 V_12V0_B2 V_12V0_B3
GND_B4 SMCLK SMDAT
GND_B7 V_3V3_B8 JTAG1_TRST# V_3V3_AUX_B10
WAKE#

A12 GND_A12 A13 REFCLK+ A14 REFCLKA15 GND_A15 A16 PER0+ A17 PER0A18 GND_A18 NC A19 RSVD_A19 A20 GND_A20 A21 PER1+ A22 PER1A23 GND_A23 A24 GND_A24 A25 PER2+ A26 PER2A27 GND_A27 A28 GND_A28 A29 PER3+ A30 PER3A31 GND_A31 NC A32 RSVD_A32

RSVD_B12 GND_B13 PET0+ PET0GND_B16
PRSNT2#_B17 GND_B18 PET1+ PET1GND_B21 GND_B22 PET2+ PET2GND_B25 GND_B26 PET3+ PET3GND_B29
RSVD_B30 PRSNT2#_B31
GND_B32

MTG1 CASE1

GND

FCI_10141523-121Y

CASE2

+12V_S

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
B12 NC
B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
MTG2

+3.3V_S +3.3V_A

0ohms 1%

DNI

0ohms 1%

DNI

ICT1

WAKE0_G2_2# 0ohms 1%

R31 0402 R32 0402

PCIe_CLK_SCL PCIe_CLK_DAT

COM COM

Not connecting SMBus on connectors

to COM-HPD main SMBus due to the

inability to garantee unique SMBus

addresses

R27 WAKE0# 0402

COM

PCIe40_TX+ PCIe40_TX-

COM COM

PCIe41_TX+ PCIe41_TX-

COM COM

PCIe42_TX+ PCIe42_TX-

COM COM

PCIe43_TX+ PCIe43_TX-

COM COM

EPRBRK_G2_2# PCIe_CLKREQ_G2_2#
Signal can also be used as a present

GND

+3.3V_S

0402 R12

R13 0402

EPRBRK_G2_2# Open Drain Output Signal

10Kohms 1%

25V 0.1uF

0402 C12

Optional

1% 10Kohms

U3 5 VCC

NC 1 NC

4

2

3 GND

GND

74LVC1G07

GPIO_EPRBRK_G2_2# Driven from any source os GPIO logic

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Reference Schematics and Block Diagrams Figure 23: PCIe x4 Slot Card Site on PCIe Group 2 PCIe Lanes 44:47

+12V_S

+3.3V_S

+3.3V_S

+3.3V_A

C2 7343-31 C5 1210 C10 0603

100uF 25V PTA
100uF 10V X6S
10uF 16V X6S

ICT7

ICT8

ICT9

ICT10

GND

GND

GND

PCI_RESET_G2_3#

COM COM
COM COM

PCIe_CLK_G2_3+ PCIe_CLK_G2_3-
PCIe44_RX+ PCIe44_RX-

COM COM

PCIe45_RX+ PCIe45_RX-

COM COM

PCIe46_RX+ PCIe46_RX-

COM COM

PCIe47_RX+ PCIe47_RX-

+12V_S

A1 PRSNT1#

A2 V_12V0_A2

GND

A3 V_12V0_A3

A4 GND_A4

A5 JTAG2_TCK

A6 JTAG3_TDI

A7 JTAG4_TDO

A8 JTAG5_TMS

A9 V_3V3_A9

A10 V_3V3_A10

A11 PERST#

J3
V_12V0_B1 V_12V0_B2 V_12V0_B3
GND_B4 SMCLK SMDAT
GND_B7 V_3V3_B8 JTAG1_TRST# V_3V3_AUX_B10
WAKE#

A12 GND_A12 A13 REFCLK+ A14 REFCLKA15 GND_A15 A16 PER0+ A17 PER0A18 GND_A18 NC A19 RSVD_A19 A20 GND_A20 A21 PER1+ A22 PER1A23 GND_A23 A24 GND_A24 A25 PER2+ A26 PER2A27 GND_A27 A28 GND_A28 A29 PER3+ A30 PER3A31 GND_A31 NC A32 RSVD_A32

RSVD_B12 GND_B13 PET0+ PET0GND_B16
PRSNT2#_B17 GND_B18 PET1+ PET1GND_B21 GND_B22 PET2+ PET2GND_B25 GND_B26 PET3+ PET3GND_B29
RSVD_B30 PRSNT2#_B31
GND_B32

MTG1 CASE1

GND

FCI_10141523-121Y

CASE2

+12V_S

+3.3V_S

B1

+3.3V_A

B2

B3

B4 B5

0ohms 1%

DNI

R29 0402

PCIe_CLK_SCL

COM

B6 B7 B8

0ohms 1%

DNI

R30 PCIe_CLK_DAT

COM

0402 Not connecting SMBus on connectors

B9

ICT6

to COM-HPD main SMBus due to the inability to garantee unique SMBus

B10

addresses

B11

WAKE0_G2_3# 0ohms

1%

R26 WAKE0# 0402

COM

B12 NC
B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
MTG2

PCIe44_TX+ PCIe44_TX-

COM COM

PCIe45_TX+ PCIe45_TX-

COM COM

PCIe46_TX+ PCIe46_TX-

COM COM

PCIe47_TX+ PCIe47_TX-

COM COM

EPRBRK_G2_3# PCIe_CLKREQ_G2_3#
Signal can also be used as a present

GND

+3.3V_S

0402 R15

R25 0402

EPRBRK_G2_3# Open Drain Output Signal

10Kohms 1%

25V 0.1uF

0402 C13

Optional

U4 5 VCC
4

NC 1 NC 2

1% 10Kohms

GPIO_EPRBRK_G2_3#

3 GND

GND

74LVC1G07

Driven from any source os GPIO logic

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Reference Schematics and Block Diagrams Figure 24: PCIe Clock Buffer and Reset Buffer for PCIe Group 2 Example

PCIe_CLKREQ_G2_1# PCIe_CLKREQ_G2_2# PCIe_CLKREQ_G2_3#

COM COM

PCIe_REFCLK2+ PCIe_REFCLK2-

+3V3_S +1V8_S

PCIe_CLK_SCL PCIe_CLK_SDA

0ohms 1%

DNI

R36 0402

0ohms 1%

DNI

R35 0402

PCIe_CLKREQ_G3_0#

GND

U22 10 SCLK 11 SDATA 32 SADR_TRI
1 BW_SEL_TRI 31 PD#
12 OE0# 17 OE1# 24 OE2# 29 OE3#
5 IN+ 6 IN-
15 GND1 26 GND2 30 GND3
8 GND_DIG 7 GND_R 20 GND_A
PI6CB18401ZH1EX +1V8_S

C40 0603 C33 0402 C34 0402 C35 0402 C36 0402 C37 0402

VDD_DIG 9 VDD_R 4
VDD_O1 16 VDD_O2 25
VDD_A 21 Q0+ 13 Q0- 14

+1.8V_S +1.8V_S_PI6CB148401

0402 C31 0603 C39

25V 0.1uF
10V 10uF

PCIe_CLK_G2_0+ PCIe_CLK_G2_0-

GND GND

Q1+ 18 Q1- 19

PCIe_CLK_G2_1+ PCIe_CLK_G2_1-

Q2+ 22 Q2- 23

PCIe_CLK_G2_2+ PCIe_CLK_G2_2-

Q3+ 27 Q3- 28

PCIe_CLK_G2_3+ PCIe_CLK_G2_3-

NC1 2 NC NC2 3 NC

+1.8V_S

R59 0402

+1.8V_S 1ohms 1%

0402 C32

25V 0.1uF

GND
ICT17 ICT18

GND GND GND GND GND GND

R42 0402 R44 0402 R46 0402 R48 0402 R50 0402 R54 0402 R52 0402
10uF 10V 0.1uF 25V 0.1uF 25V 0.1uF 25V 0.1uF 25V 0.1uF 25V

PCIe_CLKREQ_G2_3# PCIe_CLKREQ_G2_2# PCIe_CLKREQ_G2_1# PCIe_CLKREQ_G3_0# PCIe_G2_CLKPD# BW_SEL_TRI_G2 SADR_TRI_G2
+1V8_S

0402

0402

0402

10Kohms 1%
10Kohms 1%
10Kohms 1%
10Kohms 1%
10Kohms 1%
10Kohms 1%
10Kohms 1%

0402

0402

R55 0402

0402

SADR: SMBUS ADDR 0 0x6B (7-bit) M 0x6C (7-bit) 1 0x6D (7-bit)
BW_SEL_TRI 0 LOW BW MODE M BYPASS MODE (Default) 1 HIGH BW MODE

10Kohms DNI R53

10Kohms DNI R51

10Kohms DNI R49

10Kohms DNI R47

10Kohms DNI R45

10Kohms DNI R43

C7 0402

R1 0402 C8 0402

1%

10Kohms 1%

1%

1%

1%

1%

1%

0.1uF 25V

10Kohms 1% 0.1uF 25V

COM PCIe_CLKREQ2#

U2 5 VCC 4
3 GND

NC 1 NC 2

U1 5 VCC 4
2 GND

1 GND
3 6

GND

SN74LVC1G07

GND

SN74LVC1G11

+3.3V_S

U7

1

VCC 5

22ohms 1%

R39 0402

PCI_RESET_G2_1#

1

COM

PLTRST#

2

1

4

22ohms 1%

R37 0402

PCI_RESET_G2_2#

2

GND

GND 3

0.1uF 25V

C29 0402

22ohms 1%

R38 0402

PCI_RESET_G2_3#

3

74LVC1G125

GND

*Max 4 outputs per buffer *Push/Pull design use LVC07 wih PU resistor for OC designs

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Reference Schematics and Block Diagrams

3.6.7.

MXM-3 Graphics Card Module on Carrier

The COM Express Carrier Design Guide Rev 2.0 Section 2.6 has a good schematic example of a MXM-3 graphics card implementation on COM Express Carriers. The net names used are not the same as the COMHPC net names, but the correlation is straightforward.
MXM-3 cards use a 16 lane PCI Express interface. Most MXM cards also allow x8 implementations (and all PCIe devices must work in x1 configurations per the PCI-SIG specification). COM-HPC recommends but does not require that COM-HPC PCIe Group 1 be used for PEG (PCI Express Graphics). No Carrier PCIe clock buffer is needed for the MXM card (assuming that the MXM card is only PCIe device used in the COMHPC PCIe Group). The COM-HPC PCIe reference clock that goes with the COM-HPC PCIe group can be used directly with the MXM card.
Coupling capacitors for the COM-HPC Module PCIe RX pairs (MXM card PCIe TX pairs) must be present on the Carrier, preferably close to the MXM connector. Use discrete 0402 or 0201 package size parts.
The MXM-3 specification document is currently hard to find. The document was created and is owned by Nvidia but is not publicly available. Information found in the COM Express Carrier Design Guide, from the MXM-3 connector vendors (Aces, Amphenol / FCI, Foxconn, JAE, Yamaichi), from the MXM GPU card vendors and from the COM-HPC Module vendor should be sufficient to carry out a design.
The Amphenol / FCI MXM-3 connector part number 10151114-001TLF supports all PCIe signal rates up to and including Gen 5.
Note that MXM cards operate in the S0 power domain only. Any signals that are active in the S5 (suspend) power state must be isolated, in the S5 power state, from the MXM card.
Note also that MXM-3 connectors have 314 individual pins, but the MXM-3 specification gangs multiple connector pins together for power delivery. The 314 individual connector pins are grouped together in the NVIDIA MXM-3 specification into PWR and GND blocks labeled E1, E2, E3 and E4, and then the pins left over are numbered 1 through 281. The MXM-3 connector drawings from the connector vendors usually illustrate this.

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Reference Schematics and Block Diagrams

3.6.8.

PCIe Reference Clocks

COM-HPC, like COM Express and like most commercial and embedded PCI Express implementations, uses the "Common Clock" architecture defined in the PCI-SIG PCI Express Base Specification, Revisions 1 through 5. In this arrangement, there is a common 100 MHz reference clock source that feeds the PCIe Root complex and copies are fed to each PCIe Target device serviced by that Root. The maximum skew allowed between any two PCIe reference clocks, at their destinations, is 10 ns for PCIe Gen 1 and 12 ns for Gen 2 through 5.
In most cases, the 100 MHz reference source is integrated into the SOC or chipset and the reference clock routing to the Root is internal to the SOC or chipset. In some cases, a clock generator IC that is external to the SOC or chipset is used. In any case, the 100 MHz reference source for a COM-HPC Root device is on the COM-HPC Module, either internal or external to the SOC or chipset.
The SOC or chipset may provide one or multiple copies of the PCIe reference clock. If the SOC, chipset or Module does not provide enough copies of the reference clock for the Carrier PCIe targets then one or more PCIe clock buffers are used, on and / or off Module, depending on the situation.
The PCIe targets use the 100 MHz reference clock copy, along with the clocking information embedded into the PCIe data stream to quickly form a local copy of the appropriate high frequency clock (2.5 GHz for Gen1, 5 GHz for Gen 2, and so on) needed to correctly interpret the incoming PCIe data stream, and to correctly time and encode the target's outgoing data stream.
Table 6 below lists the maximum clock jitter allowed for each PCIe generation, per the PCI-SIG source specifications, for the Common Clock architecture. Note the ever shrinking jitter allowance as the generations advance. For example, the Gen 5 jitter allowance is only 15% of the Gen 3 allowance. However, PCIe Gen 5 uses a different filtering transfer function than Gen 3 and Gen 4, so the comparison is more nuanced than indicated here.

Table 6: PCIe Maximum Allowable Clock Jitter

PCIe

Signaling

Generation Rate

1

2.5 Gbps

2

5.0 Gbps

3

8.0 Gbps

4

16.0 Gbps

5

32.0 Gbps

6

64.0 Gbps

Reference Clock Max Jitter Allowed
86 ps PTP 3.1 ps RMS 1.0 ps RMS 0.5 ps RMS 0.15 ps RMS 0.10 ps RMS

Notes
PTP is Peak to Peak RMS is Root Mean Square

Table 7 on the following page defines some PCIe Clock Buffer mode terminology.

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Reference Schematics and Block Diagrams

Table 7: PCIe Clock Buffer Modes

Mode

Description

Pros and Cons

Zero Delay

A Clock Buffer PLL keeps the output clock copies in phase with the input clock.
Also known as ZDB (Zero Delay Buffer) mode or as PLL mode.
Some clock buffers have High Bandwidth and Low Bandwidth PLL modes.

Pro: Zero delay makes it easier to meet the maximum skew of 12 ns between any two clocks, especially if the PCIe traces are very long, or if buffers are cascaded
The PLL tends average out the jitter contribution from the source clock (see jitter discussion later in this document section, following Table 8)

Con: PLLs buffers may have trouble with a Spread Spectrum source (see discussion following Table 8)

Fan Out or PLL Bypass No PLL used. The output clock copies are an Pro: lower jitter from the buffer

exact frequency copy of the input but are not in itself, in most cases (but the

phase with the input.

source clock jitter must be added

to the that of the fan out buffer,

per discussion following Table 8)

Fan out buffers track a SpreadSpectrum clock source easily

Con: may be harder to meet 12 ns max clock skew

Although the fan out buffer jitter itself is low, the source clock jitter adds to the fan out buffer jitter

Timing Delay Discussion For Various PCIe Clock Buffer Scenarios
Regarding the max PCIe Reference Clock skew of 12 ns (or 10 ns for PCIe Gen 1) and the use of Fan Out (non ­ PLL) based clock buffers: a modern Fan Out buffer will have a worst case skew of well under 5 ns (several vendors claim 3 ns max, and at least one claims 1.5 ns max). Signals propagate at about 6 inches per ns, so a system with a 5 ns buffer delay and about 12 inches of PCB trace (2 ns delay) would have a worst case skew of 7 ns which is comfortably within the 12 ns Gen 2 through Gen 5 skew limit. Very long PCIe trace situations might need the Zero Delay Buffer ­ be aware of the possible issues with spread spectrum sources.
However .. if there is a clock buffer on the COM-HPC Module in-between the Root complex PCIe reference clock and the clock(s) going out to the COM-HPC pins, then there will likely be an additional delay time that factors into the analysis in the previous paragraph. Check with your Module vendor on that. As: "what is the skew between the PCIe Reference Clock to the CPU or SOC Root Complex, and the COM-HPC PCIe Clock Reference pins" ... it could be anywhere from 0 ns to 5 ns, depending on Module design details. Also: "what is the jitter contribution of a Module PCIe clock buffer" - if there is one.

PCIe Clock Buffer Options ­ Keep Them Open
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A PCIe Clock Buffer IC usually has pin-strap(s) and / or SMBus options allowing the Clock Buffer operational modes to be set. It is best to keep access to these options open as sometimes issues can be resolved late in the design cycle (i.e. during regulatory and compliance testing) by changing the operational mode of the PCIe Clock Buffer. For example, Spread Spectrum PCIe reference clock operation may work with some but not all of the Clock Buffer modes. Additionally, some PCIe Clock Buffer devices have mechanisms (such as SMBus registers or OTP ordering options) to change parameters such as output clock slew rate, signal amplitude and / or the output termination values.

Sample PCIe Clock Buffer List
A sample collection of PCIe Clock Buffers is given in Table 8 below. Of course this is just a snapshot of what is available and appropriate at the time of this writing. Fan Out Mode jitter is additive (meaning the Module source jitter needs to be added together with the Fan Out buffer jitter). PLL Mode jitter is not additive, hence is marked as Total in the Table. The Module source jitter tends to get averaged out in the PLL. This is described in more detail on the page following Table 8.

Table 8: PCIe Clock Buffer Vendors and Part Numbers

Vendor Diodes Inc. (Pericom)
Diodes Inc. (Pericom)
Diodes Inc. (Pericom)
Renesas (IDT)
Renesas (IDT)

Part Numbers

Notes

RMS Jitter (picoseconds)

PI6CB18200 (dual, no internal term)

PCIe Gen 4 capable

PLL Mode (Total)

PI6CB18401 (quad, internal term)

1.8V supplies

Gen 1 5.0

PI6CB18601 (hex, internal term)

OE# on each output

Gen 2

0.3

PI6CB18801 (octal, internal term)

SMBus configuration option

Gen 3

0.1

Pin strap configuration option

Gen 4

0.05

A internal termination value for 100 ohm dif- Zero Delay Buffer modes

ferential traces is implied in the data sheet

High BW PLL

Fan Out Mode

but not explicitly stated.

Low BW PLL

Values not shown in

PLL Bypass (aka Fan Out) Mode public data sheet

PI6CB33202 (dual, 85 ohm internal term) PI6CB33402 (quad, 85 ohm internal term) PI6CB33602 (hex, 85 ohm internal term) PI6CB33802 (octal, 85 ohm internal term)
PI6CB33201 (dual, 100 ohm internal term) PI6CB33401 (quad, 100 ohm internal term) PI6CB33601 (hex, 100 ohm internal term) PI6CB33801 (octal, 100 ohm internal term)

PCIe Gen 5 capable

PLL Mode (Total)

3.3V power supply

Gen 1 0.05

OE# on each output

Gen 2 0.05

SMBus configuration option

Gen 3 0.05

Pin strap configuration option Gen 4 0.05

Zero Delay Buffer modes

Gen 5 0.05

High BW PLL

Low BW PLL

PLL Bypass (aka Fan Out) Mode

PI6CB332001A (20 outputs, 85 ohm internal PCIe Gen 5 capable

Fan Out (Additive)

term)

3.3V power supply

Gen 1 0.03

OE# for 8 outputs

Gen 2 0.03

SMBus, Side-Band interface sup- Gen 3 0.03

port

Gen 4 0.03

20 HCSL outputs with On-chip Gen 5 0.12

Termination

9DBL0252 (dual, 85 ohm internal term) 9DBL0452 (quad, 85 ohm internal term) 9DBL0651 (hex, 85 ohm internal term) 9DBL0851 (octal, 85 ohm internal term)
9DBL0242 (dual, 100 ohm internal term) 9DBL0442 (quad, 100 ohm internal term) 9DBL0641 (hex, 100 ohm internal term) 9DBL0841 (octal, 100 ohm internal term)

PCIe Gen 5 capable

Fan Out (Additive)

3.3V power supplies

Gen 1 5.0

OE# on each output

Gen 2 0.428

SMBus configuration option

Gen 3 0.149

Pin strap configuration option Gen 4 0.156

Zero Delay Buffer modes

Gen 5 0.05

High BW PLL

Low BW PLL

PLL Mode (Total)

PLL Bypass (aka Fan Out) Mode Gen 1 33

Gen 2 1.9

Gen 3 0.53

Gen 4 0.48

Gen 5 0.149

9DBL0255 (dual, 85 ohm internal term) 9DBL0455 (quad, 85 ohm internal term)

Ultra low jitter PCIe Gen 5 capable

Fan Out (Additive) Gen 3 0.033

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Vendor

Part Numbers

Notes

RMS Jitter (picoseconds)

100 ohm option with ext resistors Gen 4

3.3V power supplies

Gen 5

OE# for each output

0.033 0.012

Renesas (IDT)
Skyworks (Silicon Labs)

9ZXL0451E (quad, 85 ohm internal term) 9ZXL0651E (hex , 85 ohm internal term) 9ZXL0851E (octal, 85 ohm internal term) 9ZXL1251E (12 out, 85 ohm internal term)

PCIe Gen 5 capable

Fan Out (Additive)

3.3V power supplies

Gen 1 1.9

OE# on each output

Gen 2 0.126

SMBus configuration option

Gen 3 0.062

Zero Delay Buffer modes

Gen 4 0.062

High BW PLL

Gen 5 0.024

Low BW PLL

PLL Bypass (aka Fan Out) Mode Low BW PLL Mode

(Total Jitter)

Gen 1 6.8

Gen 2 0.12

Gen 3 0.07

Gen 4 0.07

Gen 5 0.018

Si53204-A02 (quad, 85 ohm internal term) PCIe Gen 5 capable Si53208-A02 (octal, 85 ohm internal term) 1.8V power supplies Si53212-A02 (12 out, 85 ohm internal term) OE# on each output
SMBus configuration option Si53204-A01 (quad, 100 ohm internal term) Fan Out Mode only (no PLL) Si53208-A01 (octal, 100 ohm internal term) Si53212-A01 (12 out, 100 ohm internal term)

Fan Out (Additive) Gen 1 17 (PTP) Gen 2 0.2 Gen 3 0.06 Gen 4 0.06 Gen 5 0.021

Texas Instruments

Silicon Labs has many other PCIe Clock Buffers, too numerous to list here. LMK00334 (quad output, external term)

Texas

LMK00338 (octal output, external term)

Instruments

Texas

CDCB2000 (20 outputs, 85 ohm int term)

Instruments

Texas

CDCDB800 (octal output, 85 or 100ohm

Instruments

software selectable term)

PCIe Gen 4 capable 3.3V and 2.5V supplies Single OE# Fan Out Mode only

Fan Out (Additive) Gen 3 0.15 Gen 4 0.05

PCIe Gen 3 capable 3.3V and 2.5V supplies Single OE# Fan Out Mode only

Fan Out (Additive) Gen 3 0.15

PCIe Gen 5 capable

PLL Mode (Total)

3.3V supplies

Gen 1 5.0

OE# for 8 outputs

Gen 2 0.2

SMBus configuration option

Gen 3 0.15

Side Band Interface config option Gen 4 0.08

Gen 5 0.03

PCIe Gen 5 capable

Fan Out (Additive)

3.3V supplies

Gen 3 0.1

OE# on each output

Gen 4 0.1

SMBus configuration options

Gen 5 0.025

Fan Out Mode only

Propagation delay 0.5 ns typically

3 ns max

There may be more subtleties in the jitter numbers than is immediately apparent here. For example, some buffers allow the clock output slew rate to be adjusted, but the slew rate may in turn affect the jitter values. Check the vendor data sheets and make use of the vendor application engineers.

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Note on the Additive and Total Jitter values in Table 8 Above: These values are taken from silicon vendor data sheets and are meant here as a rough guide. The jitter values for all operational modes (e.g. high PLL BW, low PLL BW etc) of the clock buffer devices may not be shown here. The values in the Table for Fan Out buffers are the "Maximum Additive Jitter" values listed in the vendor data sheets. For PLL buffers, the typical values are usually much lower, often less than half, of the maximum values. Jitter analysis can be tricky. Designers should consult the actual vendor data sheets and vendor application notes before making design decisions.
Note on Fan ­ Out Buffer Jitter vs. PLL or Zero Delay Buffers If a Fan-Out mode PCIe clock buffer is used, then the clock jitter at the target is the square root of the sum of the squares of the COM-HPC Module clock source and of the Fan-Out buffer jitter, per the expression shown here:

For PLL or Zero ­ Delay mode buffers, the clock jitter at the target is simply the jitter of the PLL buffer as listed

in the vendor data sheet. The PLL buffer tends to average out the source clock jitter, unless it is

extreme.

In other words, with regard to the jitter values shown in Table 8 above, the Fan-Out buffer jitter values are not the full story, as the clock generator source jitter values need to be factored in per the equation above. The source clock generator jitter values need to be obtained from the Module vendor or the SOC vendor data sheets.

Note on the Internal Termination Impedances in Table 8 Above:
PCIe Clock Buffer internal output termination values suitable for both 85 ohm and 100 ohm differential traces are shown as being available in Table 8 above. The COM-HPC Base Specification recommends an 85 ohm differential impedance for the PCIe Reference Clocks coming off the Module, and hence into the Carrier Clock Buffer. Designers are free to choose either 85 ohms or 100 ohm differential impedances for their Clock Buffer output distribution. The phrasing "85 ohm internal term" in the Table above means that the device internal termination is appropriate for 85 ohm differential pairs, and similarly for "100 ohm internal term".

Spread Spectrum Clock (SSC) Operation
SSC profiles for different PCIe generations are different, so a PLL based buffer with support for SSC needs to have an appropriate loop bandwidth for the PFD (Phase Frequency Detector) within the PLL. Therefore, it is advisable to check whether a PLL based buffer supports SSC for the PCIe generation it is to be used with.
Some clock buffer vendors recommend against using a Spread Spectrum Clock source with their PLL mode parts and recommend the use of a Fan Out buffer instead. Check with your clock buffer vendor and allow for a PLL bypass mode (Fan Out Mode) option if possible.

COM-HPC Reference Clocks vs COM Express / Use of Clock Buffers
COM Express Rev 3.0 defines a single PCIe Reference Clock in it's pinout.
COM-HPC Rev 1.0 allows up to five PCIe Reference Clock pairs ­ there is one COM-HPC Module PCIe Reference Clock pair for each of the five COM-HPC PCIe groups, as outlined in Section 3.6.1. above.

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3.6.9.

PCIe Redrivers and Retimers

PCIe maximum trace length guidelines are given in Section 4.3.4. below and are presented along with loss budgets and more context in the COM-HPC Base Specification. However, PCIe Gen 3, 4, and 5 implementations may well need a redriver or retimer on the Carrier to make up for signal degradation.
A redriver is an analog circuit that reshapes the PCIe signal using sophisticated analog techniques. A nearly closed PCIe signal eye can become a compliant open eye with a redriver. Redrivers may have a digital section in the form of I2C accessible registers or strap pins to set redriver parameters.
A retimer is a digital and analog circuit that clocks in the PCIe signal using the PCIe 100 MHz reference clock and an on-chip PLL and reissues the reclocked signal in pristine form. Two popular vendors for PCIe redriver and retimer products are Diodes Inc. (formerly Pericom) (www.diodes.com) and Texas Instruments (www.ti.com). A retimer may possibly yield better results than a redriver, at a cost.

Table 9: PCIe Redrivers and Retimers

Vendor

P/N

Notes

Diodes Inc Texas Instruments

PI3EQX16904GL PI3EQX16908GL DS160PR410 DS160PR810 DS160PT801 DS320PR810 DS320PR822

PCIe Gen 4 capable quad lane redriver (4 lanes in one direction) PCIe Gen 4 capable octal lane redriver (8 lanes in one direction) PCIe Gen 4 capable quad lane redriver (4 lanes in one direction) PCIe Gen 4 capable octal lane redriver (8 lanes in one direction) PCIe Gen 4 capable 16 lane retimer (8 lanes TX and 8 lanes RX) PCIe Gen 5 capable octal lane redriver (8 lanes in one direction) PCIe Gen 5 capable quad 2x2 crosspoint redriver

The items shown in Table 9 above represent only a small sample of parts available on the market. Texas Instruments, for example, has quite a few additional redriver and retimer parts not listed here. Some of the unlisted parts incorporate redriver or retimer functions along with analog multiplexer and cross-point switch functions.

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3.7. 3.7.1.

USB USB Terms and General Information

Table 10: USB.org Branding Term Summary

USB.org

Nominal Bit

Current Branding Rates

Notes

USB.org Former Branding

USB 2.0 USB 3.2 Gen 1

480 Mbps

Single half duplex DC coupled pair

(High Speed mode) Also supports slower USB 1.1 and 1.0 legacy modes

5 Gbps

Dual simplex AC coupled transmit pair and a receive pair. Also requires a specific USB 2.0 link, on a separate set of conductors.

USB 2.0
USB 3.0 USB 3.1 Gen 1

USB 3.2 Gen 2

10 Gbps

Dual simplex AC coupled transmit pair and a receive pair. Also requires a USB 3.1

specific USB 2.0 link, on a separate set of conductors.

USB 3.1 Gen 2

USB 3.2 Gen 2x2 USB4 Gen 2x2 USB4 Gen 3x2
USB SuperSpeed USB SuperSpeed+

10 Gbps (per lane) Two AC coupled transmit pairs and two receive pairs allowing 20 Gbps

20 Gbps (two

operation in each direction. Also requires a specific USB 2.0 link, on a sep-

lanes)

arate set of conductors.

10 Gbps (per lane) Incorporates USB 3.2 Gen 2x2 and USB 2.0 features, along with addi-

20 Gbps (two

tional features such as DisplayPort operation, USB Type-C (reversible)

lanes)

connector, and Thunderbolt 4 support.

20 Gbps (per lane) 40 Gbps (two lanes)

Features 20 Gbps bit rate per lane and uses 2 lanes TX and 2 lanes RX. Also includes USB 2.0 features, along with additional features such as DisplayPort operation, USB Type-C (reversible) connector, and Thunderbolt 4 support.

5 Gbps 10 or 20 Gbps

The high speed interface used in USB 3.2 Gen 1, Gen 2, Gen 2x2 and USB4 is referred to as the SuperSpeed or SuperSpeed+ interface. A USB 3.2 Gen 1, Gen 2, Gen 2x2 or USB4 implementation require both SuperSpeed / SuperSpeed+ support and USB 2.0 support. The SuperSpeed / SuperSpeed+ interface is implemented on a separate set of pins from the USB 2.0 interface. However, every SuperSpeed implementation needs a specific companion USB 2.0 interface.

Actual payload data rates are lower than what is implied by the "Nominal Bit Rates" in the chart above, due to the encoding methods used in the serialized data stream.
The most common connector for USB host ports is the Type-A connector. Figure 25 below is a view looking into a USB 3 Type-A host receptacle (the Carrier connector is receptacle, the cable connector is the plug). Some points about this illustration:
· A USB 2.0 Type-A connector only has pins 1 through 4 present. Pin-out details are in Table 11 below. · A USB 3 Type-A connector has 9 pins:
 Pins 1 through 4 from the USB 2.0 definition are used for power, GND and a USB 2.0 data pair.  Pins 5 through 9 are used for SuperSpeed or SuperSpeed+ TX and RX pairs and a GND. · A USB 2.0 cable plug may be used with a USB 3 receptacle, but only the USB 2.0 link will function. · A USB 3 cable plug may be used with a USB 2.0 receptacle, but only the USB 2.0 link will function.  The USB 3 pins 5 through 9 are cleverly positioned so that they are invisible to the USB 2.0 plug. · USB 2.0 target devices are allowed to consume up to 500 mA at 5V on a Type-A connector. · USB 3 target devices are allowed to consume up to 900 mA at 5V on a Type-A connector.

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Figure 25: USB 3 Type-A Connector Receptacle ­ Looking Into the Receptacle

9

8

7

6

5

1

2

3

4

Table 11: USB Type-A Pin-Out Pin Signal Signal Description

1 VBUS 5V current limited USB target power

2 D-

USB 2.0 differential signal (-)

3 D+

USB 2.0 differential signal (+)

4 GND

GND for USB 2.0 pair and power

5 SSRX- USB SuperSpeed RX(-)

6 SSRX+ USB SuperSpeed RX(+)

7 GND

GND for SuperSpeed RX and TX cable drain wire

8 SSTX- USB SuperSpeed TX(-)

9 SSTX+ USB SuperSpeed TX(+)

Notes 500mA (USB 2) or 900mA (USB 3)
Not used / not present on USB 2.0 Not used / not present on USB 2.0 Not used / not present on USB 2.0 Not used / not present on USB 2.0 Not used / not present on USB 2.0

Type-A Connector Electrical Distinctions There are three general categories of USB Type-A connectors:

· USB 2.0 · USB 3.2 Gen 1 · USB 3.2 Gen 2

480 Mbps USB 2.0 signaling (no USB 3) ­ 4 pin connector 5 Gbps SuperSpeed signaling (along with USB 2.0) - 9 pin connector
10 Gbps SuperSpeed+ signaling (along with USB 2.0) ­ 9 pin connector

For USB 2.0 and USB 3.2 Gen 1 Type-A connectors, there are many vendors and styles (R/A, vertical, single, dual, quad combinations, combinations with other standards such as GbE etc).
For USB 3.2 Gen 2 (10 Gbps pair signaling), there are not many Type-A connector parts available as of this writing. Amphenol FCI is a connector vendor that has several 10 Gbps capable Type-A connectors available. Amphenol FCI GSB4111312HR, for example is a single R/A version of such a part.
Most USB 3.2 Gen 2 implementations use a Type-C connector rather than Type-A. Type-C implementations are covered in Sections 3.7.5. through 3.7.11. below.

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3.7.2.

USB 2.0 Type-A Example

Figure 26:
+5V_A C201 C202 1u 16V 100n 25V 0402 0402
+5V_A C206 C207 1u 16V 100n 25V 0402 0402

USB 2.0 Type-A Example

R155
10K 0402

U32 1 VIN

VOUT 6

2 GND

ILIM 5

3 EN

FAULT# 4

RT9728AHGE

43K 0402 R156

C203

BLM18PG121SN1J

FB7

+5V_USB5

C204

150u 10V Size C

100n 25V 0402

D32 ESD9X5.0ST5G

R2138

0 0402 EN_RSMRST

R157
10K 0402

U33 1 VIN

VOUT 6

2 GND

ILIM 5

3 EN

FAULT# 4

RT9728AHGE

R2140

0 0402 EN_RSMRST

USB5- COM USB5+ COM

43K 0402 R158

C205

BLM18PG121SN1J

FB8

+5V_USB4

C208

150u 10V Size C

100n 25V 0402

COM USB45_OC#

USB4- COM USB4+ COM D34 ESD9X5.0ST5G

DLW 21HN900SQ2 T10

USB5_N USB5_P

DLW 21HN900SQ2 T9

USB4_N USB4_P

+5V_A

RSMRST_OUT# COM

5
R2147 100K 0402

4

3

R2146 4.7K 0402
2

6

EN_RSMRST
Q76A 2N7002DW

1

Q76B 2N7002DW

D33

5 VDD 2 GND 7 PAD

1 CH1 3 CH2 4 CH3 6 CH4

DRTR5V0U4LP16

USB5_N USB5_P USB4_P USB4_N

CN20

TE 5787745

UPPER USB

1 2 3 4

+5VA DD+ GNDA

LOWER USB

5 6 7 8

+5VB DD+ GNDB

SH(4)

9 1 0 1 1 12

SHIELD

0 R301 0603

Figure 26 above illustrates a typical USB 2.0 implementation on a Carrier.
· The USB 2.0 data lines must be routed as differential pairs, in a no-stub fashion. · Components T9 and T10 are common-mode chokes that are an EMI mitigation measure. · Component D33 is a ESD protection diode array. Pins 1,3,4,6 may be exchanged if needed to provide the
easiest no-stub routing. · Components U32 and U33 are USB power switches and current limiters. For USB 2.0, the current deliv-
ered to a USB target device is to be limited to about 500 mA.  The power switch / current limiter shown is from Richtek. There are many similar parts available from
Texas Instruments, Micrel, Microchip and others. · The current limiter IC FAULT# pins are tied to the COM Module USB port 4 and 5 over-current input. There
are 4 such inputs (for USB 0,1 and USB 2,3 and USB 4,5 and USB 6,7). · The 5V power traces involved between the USB power switches, through FB7 and FB8 and on to connec-
tor CN20 must be sized to carry the 1A current (and this should be increased to 1.5 or 2 A to allow for a safety factor). · The power switches are enabled by the COM-HPC RSMRST_OUT# signal. This signal going high indicates that the +5V_A power rail is stable.

USB 2.0 Allocation Note
The COM-HPC Client and Server pin-outs allow up to eight USB 2.0 ports each. Note however that the first four USB 2.0 ports (COM-HPC USB0+/- through USB3+/-) are paired with the corresponding USB SuperSpeed ports (COM-HPC USB0_SSTX0+/- and USB0_SSRX0+/- through USB3_SSTX0+/- and USB3RX0+/-). A USB SuperSpeed port needs a specific companion USB 2.0 pair for certain setup functions.
Thus ... if the Carrier needs one or more USB 2.0 only ports (no SuperSpeed) in addition to the four SuperSpeed capable ports, the above pairings need to be considered. COM-HPC USB4+/- through USB7+/- are USB 2.0 only ports.

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3.7.3.

USB 3.2 Gen 1 and Gen 2 Type-A

A USB 3.2 Gen 1 example on a Type-A connector is given in the COM Express Carrier Design Guide Rev 2.0 Section 2.9. At the time that the COMe Design Guide was written, USB 3.2 Gen 1 (single SuperSpeed TX pair and single RX pair, 5 Gbps signaling, plus a USB 2.0 pair) was referred to as USB 3.0.
A USB 3.2 Gen 2 Type-A connector implementation (single SuperSpeed+ TX pair and single RX pair, 10 Mbps signaling) is basically the same as a Gen 1 implementation, except that the components involved may need an upgrade for the 10 Gbps signaling: lower capacitance ESD diodes, different common mode choke choices and a connector receptacle appropriate for 10 Gbps signaling. An additional consideration is that there may be a greater need for a redriver. Most USB 3.2 Gen 2 implementations use a Type-C connector rather than Type-A. Type-C implementations are covered in Sections 3.7.5. through 3.7.11. below.
No USB 3 redriver is shown in the COM Express Carrier Design Guide example. If the traces from the COMHPC Module connector to the Type-A host receptacle are more than a few inches, then a Carrier redriver may be advisable.

3.7.4.

USB 3 Redrivers

Table 12: USB 3 Redrivers

Vendor P/N

Notes

Diodes Inc PI3EQX7841 USB 3.1 Gen 1 capable single port redriver (1 TX pair and 1 RX pair) 5 Gbps per pair

PI3EQX1004E USB 3.1 Gen 2 capable dual port redriver (2 TX pairs and 2 RX pairs ) 10 Gbps per pair

Texas

TUSB522P USB 3.2 Gen 1 capable single port redriver (1 TX pair and 1 RX pair)

Instruments

5 Gbps per pair

TUSB1002A USB 3.2 Gen 2 capable single port redriver (1 TX pair and 1 RX pair) 10 Gbps per pair

TUSB1004

USB 3.2 Gen 2 capable dual port redriver (2 TX pairs and 2 RX pairs ) 10 Gbps per pair May be used to support two USB 3.2 Gen 2 ports

The items shown in Table 12 above represent only a small sample of such parts available on the market. USB Type-C Port Multiplexers, which may include redriver and retimer capabilities, are listed in Table 14 below. USB Type-C implementations are covered in Sections 3.7.5. through 3.7.10. below, and USB4 in Section 3.7.11. .

USB Hubs ­ May Serve as Retimers
USB 2 and USB 3 hubs are plentiful and may be considered as a form of a USB retimer: they clock the USB 2 and 3 signals in, process them and clock them out in fresh form. Of course the downstream bandwidth is shared, if more than one downstream hub port is used. Microchip Technologies (www.microchip.com) seems to be the dominant USB hub supplier and has dozens of offerings. Granted, there may be some software subtleties concerning the use of USB hubs versus true USB retimers (a true retimer should be invisible to software apart from possible setup; a hub has to be enumerated by the operating system, etc.).

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3.7.5.

USB Type-C Overview

USB Type-C refers to a small form factor reversible connector definition (reversible cable plug, no polarity, can be inserted with either orientation), and to the USB and other data and negotiated power delivery formats that it supports. Some highlights include:

· Polarity free operation

 Cable plug can be used in either orientation

· USB 2.0

( 480 Mbps signaling)

· USB 3.2 Gen 1 x1 and Gen 2 x 1

( 5 Gbps, 10 Gbps signaling) (single lane)

· USB 3.2 Gen 1 x2 and Gen 2 x 2

( 10 Gbps, 20 Gbps signaling) (2 lanes)

· "Alternate Modes" including

 DisplayPort (2 lanes) + USB 3.2

 DisplayPort (4 lanes)

 HDMI

 Intel Thunderbolt

 Other vendor specific Alternate Modes

· USB4, described Section 3.7.11. below.

· USB Power Delivery (PD) protocol and implementation

 Allows negotiated power delivery, from 5V up to 20V and up to 100W.

· Active cable support (electronics within the USB cable assembly)

For an excellent explanation of USB Type-C features, capabilities and details on how they work, see the Microchip Technologies Application Note AN1953 Introduction to USB Type-C. Much of the information in this section has been adapted from this note.
A typical Type-C receptacle is shown in Figure 27 below, at the left. A typical cable plug is shown at the right. The connector is fairly small, with an overall width less than 9mm and body height just under 3mm. These dimensions are similar but slightly larger than the Apple Computer "Lightening" connectors that are popular on consumer cell phones. The USB Type-C connector system has more capabilities than the "Lightening" system.
The receptacle and corresponding cable plugs are mechanically symmetrical and the cable plug can be used in either orientation. The connector pin-out, presented on the following page, is almost completely symmetrical.
There are some locking versions of the USB Type-C connector available.

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Figure 27: USB Type-C Receptacle and Plug Images

Reference Schematics and Block Diagrams

Figure 28: USB Type-C Receptacle Pin-Out ­ Looking Into Carrier Receptacle

A1 A2 A3 A4 A5 A6 GND TX1+ TX1- VBUS CC1 D+ GND RX1+ RX1- VBUS SBU2 DB12 B11 B10 B9 B8 B7

A7 A8 A9 A10 A11 A12 D- SBU1 VBUS RX2- RX2+ GND D+ CC2 VBUS TX2- TX2+ GND B6 B5 B4 B3 B2 B1

Note that the Type-C receptacle connector pin-out is mostly symmetrical with respect to flipping the plug connector. If the connector plug is inserted "right side up" (plug A1 to receptacle A1 etc.), all plug and receptacle signals match. If the connector plug is inserted "upside down" (plug A1 to receptacle B1 etc) then a few things must be sorted out by Carrier hardware, as explained on the following pages.

Table 13: USB Type-C Connector Pin-out
Pin Signal Signal Name Description
A1 GND A2 TX1+ SuperSpeed TX1+ A3 TX1- SuperSpeed TX1A4 VBUS Bus Power to Peripheral USB device A5 CC1 Configuration Channel 1 or VCONN A6 D+ USB 2.0 D+ A7 D- USB 2.0 DA8 SBU1 Side Band Use 1 A9 VBUS Bus Power to Peripheral USB device A10 RX2- SuperSpeed RX2A11 RX2+ SuperSpeed RX2+ A12 GND

Pin Signal Signal Name Description

B12 GND

B11 RX1+ SuperSpeed RX1+

B10 RX1- SuperSpeed RX1-

B9 VBUS Bus Power to Peripheral USB device

B8 SBU2 Side Band Use 2

B7 D-

USB 2.0 D-

B6 D+

USB 2.0 D+

B5 CC2 Configuration Channel 2 or VCONN

B4 VBUS Bus Power to Peripheral USB device

B3 RX1- SuperSpeed TX2-

B2 RX1+ SuperSpeed TX2+

B1 GND

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For the yellow shaded cells in the Table above, the `A' and `B' signals have complete symmetry and nothing at all needs to be done to sort them out if the cable plug is "upside down". The non-shaded signals need some help in the "upside down" case ­ to get the plug signals to the correct Carrier destinations. Multiplexers are involved, and, to reduce stubs and preserve signal integrity, the "right side up" signals are usually routed through multiplexers along with the "upside down". signals.
USB 2.0 D+ and D-
The USB 2.0 D+ and D- differential pair data lines are arranged in a symmetrical block in the USB Type-C pin-out definition. This arrangement has the result that no signal multiplexing is needed for "right side up" and "upside down" cable plug insertions. However, as a consequence of this arrangement, there are some short signal stubs. Since the USB 2.0 signaling rate is relatively low (480 Mbps), this is not a problem.
VBUS
VBUS is the power source provided by the host system (the COM-HPC Carrier in this case) to the attached downstream port. It can be the traditional fixed 5V current limited supply per USB 2.0 or USB 3.x, or it can be a higher voltage supply, up to 20V, and up to 100W, as negotiated by implementations following the USB Type-C Power Delivery Specification. The Power Delivery (PD) negotiation and implementation capability is optional, but necessary for higher powered peripherals. The PD negotiation happens over one of the two CC lines. Note that there are four VBUS pins and four GND pins. All eight pins should be used, to handle the possibly high power and current levels.
VCONN
VCONN is 5V nominal 1W max power source for active USB cables. Active cables have internal electronics that boost the signals carried, allowing longer cable assembles. The electronics in an Active cable may take their power from VCONN or VBUS. VCONN is routed to the receptacle CC2 pin if the plug is "right side up" or to the receptacle CC1 pin if the plug is "upside down".
CC1 and CC2 Configuration Channel Signals
The CC1 and CC2 signals serve several purposes in USB Type-C implementations:
· The CC1 and CC2 pins are used by the host system to identify whether the cable plug is inserted "right side up" or "upside down", through an analog detection process, relying on certain resistor values on the host side and on the downstream port side.
· The CC1 and CC2 signals are also used to identify the basic host power delivery requirements to the downstream peripheral. A resistor scheme and analog measurements are used to identify 5V 500 mA. 1.5A and 3A possibilities.
· The receptacle CC1 pin (if the plug connector is "rightside up") or the receptacle CC2 pin (plug connector is "upside down") may be used to negotiate the USB Type-C Power Delivery using a one ­ wire protocol defined in the USB Power Delivery Specification. This is optional but necessary if the peripheral needs a VBUS voltage over 5V.
· VCONN power is distributed to the "unused" CC pin (CC2 for plug "rightside up" and CC1 for plug "upside down").
· The Microchip application note AN1953 explains the CC1 and CC2 operational details very well.

SuperSpeed TX1+, TX1-, RX1+, RX1-
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· If the cable plug is "rightside up" then these pins are used for the USB 3.2 Gen 1 and Gen 2 single lane SuperSpeed signals, or for the first lane of a two lane implementation.
· If the cable plug is "upside down" then the cable TX1+, TX1-, RX1+ and RX1- signals land on the receptacle TX2+, TX2-, RX2+ and RX2- pins. In this case, Carrier hardware has to route these signals to the proper TX1+, TX1-, RX1+ and RX1- destinations on the Carrier board.
· In practice, a Carrier Board multiplexor is used to route the receptacle TX1 and RX1 pairs to the proper Carrier destination, as the signals are high speed and stubs must be avoided.
· In some cases, the TX1 and RX1 high speed pairs are used for "Alternate Mode" purposes. Alternate Mode use is negotiated as part of the USB Power Delivery protocol.
SuperSpeed TX2+, TX2-, RX2+, RX2-
· If the cable plug is "rightside up" then these pins may be used for the second lane set of a USB 3.2 Gen 1x2 or Gen 2x2 implementation.
· If the cable plug is "upside down" then the cable TX2+. TX2-, RX2+ and RX2- signals land on the receptacle TX1+, TX1-, RX1+ and RX1- pins. In this case, Carrier hardware has to route these signals to the proper TX2+. TX2-, RX2+ and RX2- destinations on the Carrier board.
· In practice, a Carrier Board multiplexer is used to route the receptacle TX2 and RX2 pairs to the proper Carrier destination.
· In some cases, the TX2 and RX2 high speed pairs are used for "Alternate Mode" purposes. Alternate Mode use is negotiated as part of the USB Power Delivery protocol.
· A common Alternate Mode usage of these pairs is for a DisplayPort implementation. SBU1 and SBU2
· SBU is an acronym for Side Band Use. · These are optional signals, not needed for USB only implementations. · For the DisplayPort Alternate Mode, these signals are used for the DisplayPort Aux Channel pair. · For an HDMI Port Alternate Mode, these signals are used for the HDMI I2C channel.

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3.7.6.

USB Type-C Port Multiplexers

Selecting a USB Type-C Port Multiplexer can be tricky. It is important to understand what it does, and does not do, and what software support is available. Tables 14 lays out some of the possibilities. It is best to work with the silicon vendor and Module vendor FAEs on the details. It's pretty difficult, but not impossible, to cover all the possible USB Type-C modes in a single design. All the USB Type-C Port Multiplexers listed in this Table incorporate redriver or retimer functions, reducing part count.

Table 14: USB Type-C Port Multiplexers ­ Possible Modes

Ref Mode

Notes

Possible Part(s) Part Notes

1 USB 3.2 Gen 1x1

5 Gbps signaling single SuperSpeed TX pair and single RX pair used

TUSB542 TUSB1042 TUSB1104 TUSB1142 TUSB1146 Intel JHL8040R

TUSB542 is 5 Gbps
Others are 10 Gbps capable

2 USB 3.2 Gen 2x1

10 Gbps signaling single SuperSpeed+ TX pair and single RX pair used

TUSB1042 TUSB1044 TUSB1046 TUSB1104 TUSB1142 TUSB1146 Intel JHL8040R

10 Gbps capable parts TUSB1104 is pre release

3 USB 3.2 Gen 1x2

5 Gbps signaling per pair dual SuperSpeed TX pairs and dual RX pairs used 10 Gbps net TX speed, 10 Gbps net RX speed

TUSB1104

TUSB1104 is pre release

4 USB 3.2 Gen 2x2

10 Gbps signaling per pair dual SuperSpeed+ TX pairs and dual RX pairs used 20 Gbps net TX speed, 20 Gbps net RX speed

TUSB1104

TUSB1104 is pre release

5 DisplayPort Alternate USB 3.2 Gen 1x1 or Gen 2x1 on TX1 / RX1

TUSB546A-DCI TUSB546A-DCI is 5

Mode

Two DP pairs on TX2 / RX2 (RX2 used as DP TX TUSB1044

Gbps

2 DP lanes + USB 3 pair)

TUSB1046

Separate DP Source DP sourced externally, from GPU pins

TUSB1046A-DCI Others are 10 Gbps

TUSB1146

capable

6 DisplayPort Alternate No USB 3 at all (USB 2 remains)

Mode

Four DisplayPort pairs on TX1,RX1,TX2,RX2

4 DP lanes

DP sourced externally, from GPU pins

Separate DP Source

TUSB546A-DCI TUSB546A-DCI is 5

TUSB1046A-DCI Gbps

TUSB1046

TUSB1146

Others are 10 Gbps

capable

7 DisplayPort Alternate USB 3.2 Gen 1x1 or Gen 2x1 on TX1 / RX1

TUSB544

Mode

Two DP pairs on TX2 / RX2 (RX2 used as DP TX TUSB1044

2 DP lanes + USB 3 pair)

Intel JHL8040R

DP multiplexed with USB 3 within chip-set

8 DisplayPort Alternate No USB 3 at all (USB 2 remains)

Mode

Four DisplayPort pairs on TX1,RX1,TX2,RX2

4 DP lanes

DP multiplexed with USB 3 within chip-set

TUSB544 TUSB1044 Intel JHL8040R

9 HDMI Alternate Modes

Similar to DP Alternate Modes

TUSB546

10 USB4: 20 Gbps only 11 Thunderbolt Modes

All USB3 modes USB4: 20 Gbps signaling using 2 lanes DP Alternate Modes
All USB 3 modes USB4: 20 Gbps signaling, 40 Gbps using 2 lanes DP Alternate Modes PCIe Alternate Mode

Intel JHL8040R Intel JHL8040R

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Notes on Table 14: · All the "TUSB" prefixed parts listed above are from Texas Instruments · The TUSB1104 part is, as of this writing, a pre release TI part, referenced with permission, and optimized for USB 3.2 Gen 2x2 Type-C use. · The Intel JHL8040R is a USB4 retimer part, formerly known as the "Burnside Bridge".

3.7.7.

USB Type-C Power Delivery Controllers

The USB Type-C specification is an ambitious specification with many features. For Power Delivery, the specification allows up to 100W of power, over a voltage range from 5V to 20V, to be delivered either out of the device in question or accepted into the device. For example, a laptop computer might want to provide power to an external display or printer in some situations. In a different situation, the same laptop may want to accept power from an external charger for battery recharging.
The Power Delivery options are negotiated over the USB Type-C CC lines. If there is no negotiation, than a simple old style USB 3.0 or USB 2.0 Type-A power delivery out of the COM-HPC host is assumed
Sections 3.7.10. and 3.7.11. below, and more specifically in Figures 34 and 40 below show a USB Type-C Power Delivery solution that allows 15W max power at 5V, out of the COM-HPC carrier to an external device. The Texas Instruments TPS65994 Power Delivery controller is shown. This is actually a dual part that could support two USB Type-C ports. Only one port is used in the Section 3.7.10. USB 3.2 Gen 2x2 example, and similarly for the Section 3.7.11. USB4 port example.
Higher power levels (up to 100W, voltages over 5V to 20V range), either out or into the COM-HPC Carrier are possible with other PD controllers. For example, the Texas Instruments TPS65987D device allows up to 100W power delivery, over a 5V to 20V range, out of or into the system, using integrated power FETs. The voltage level, the current level and the current direction are negotiated over the CC lines before power is applied to, or accepted from, the USB Type-C VBUS.
The TPS65994 device used in the USB 3,2 Gen 2x2 and USB4 design examples below has a provision, using external power FETs, for up to 100W to come in to the design, but this capability is not used in these examples.
There are many additional USB Type-C Power Delivery controllers available from Cypress Semiconductor (now part of Infineon), Microchip Technologies, NXP, On Semiconductor, Texas Instrruments and others.

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3.7.8.

USB Type-C Port Protection Components

It is important to protect USB Type-C port pins against accidental exposure to 20V VBUS contact, and against ESD events. The USB 3.2 Gen 2x2 and USB4 schematic examples (Sections 3.7.10. and 3.7.11. below) illustrate this.
The examples here use a Texas Instruments TPD6S300 USB Type-C Port Protector to protect the Type-C CC lines (2 pins), SBU lines (2 pins) and the USB 2.0 lines (4 pins, in the Type-C implementation). This is shown in Figures 35 and 41 below.
Note: since these examples were created, Texas Instruments has upgraded their Type-C Port Protector to the TPD6S300A and that should be used for new designs.
The high speed data pairs (2 TX pairs and 2 RX pairs, for USB, DP, HDMI etc) are protected separately in these schematic examples, using discrete low capacitance ESD diodes. This is shown in Figures 32 and 39 below.
There are many other possible USB Type-C Port Protection components, from Texas Instruments, Microchip Technologies, On Semiconductor, NXP and others.
If the COM-HPC is implementing a battery powered option, then there are battery charging and dead battery concerns to consider. Refer to the Texas Instruments and Microchip Technologies data sheets and application notes for more technical information on this.

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3.7.9.

USB 3.2 Gen 2x1 Type-C Basic Implementation

A basic USB Type-C implementation that supports USB 2.0, USB 3.2 Gen 1 x1 and USB 3.2 Gen 2x1 is straightforward. An example is presented in Figure 29 on the following page. Although this example is in block diagram format and does not include the many passive components needed for a complete design, it only requires two small ICs. This Type-C example is hardly any more complex than a traditional USB 3 Type A , design, especially if a redriver is included in the Type A design.
The example in Figure 29 includes a USB Type-C port multiplexer and USB 3 redriver in a single IC package that can be placed close to the Type-C connector receptacle to best launch the signal over the USB cable. Note that TX line coupling capacitors are needed on the redriver output pins.
The example also includes a USB Type-C Power Source controller that performs cable detection, provides cable orientation information, provides VBUS power and VCONN power and current limiting for both, along with fault detection. This part does not implement the full USB Power Delivery protocol ­ this is not necessary here as the VBUS power is limited to traditional USB 3 values of 5V nominal, 1A operational and 1.5A fault current.
An implementation that allows the full USB Type-C Power Delivery gamut (5V to 20V, up to 100W) requires a more complex Power Source or Delivery part, that implements the one-wire negotiation on the CC1 or CC2 lines (depending on cable plug insertion polarity).
There are many useful parts for USB Type-C support available from Texas Instruments, Microchip Technology, Diodes Inc. and other vendors.
Figure 29 below uses the COM-HPC USB0 port as an example (for USB 2.0 and USB 3.2 signals). Any of the first four COM-HPC USB ports (USB0 through USB3) may be used. Remember that COM-HPC USB 2 and USB 3 ports are paired together. See the notes on this in the COM-HPC Base Specification V1.0 Table 15.

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Reference Schematics and Block Diagrams Figure 29: USB Type-C Basic Implementation: USB 3.2 Gen 1 and Gen 2

COM USB0+ COM USB0-
COM USB0_SSTX0+ COM USB0_SSTX0-
COM USB0_SSRX0+ COM USB0_SSRX0-

RX PAIR MUX

TX PAIR MUX

USB Type-C Mux and Redriver USB 3.1 Gen 2 Capable (10 Gbps) Texas Inst TUSB1142 or TUSB1042
TX1+ TX1-
TX2+ TX2-
RX1+ RX1-
RX2+ RX2-

USB Type-C Receptacle

FLIP CTL0

POL# SINK#

COM USB01_OC#

5V BUS POWER

IN

OUT

CC1

FAULT#

CC2

VBUS
CC or VCONN CC or VCONN

Texas Inst TPS25820 USB Type-C Power Source Controller

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3.7.10. USB 3.2 Gen 2x2 Type-C Example Implementation
A detailed schematic example of a USB 3.2 Gen 2x2 implementation (meaning two USB SuperSpeed TX pairs and two RX pairs, each pair capable of 10 Gbps signaling) is shown in Figures 30 through 35 below. The net TX signaling over two pairs is 20 Gbps, and the net RX signalining over two pairs is 20 Gbps This is delivered over a Type-C reversible connector.
The Type-C port multiplexer shown in Figure 31 below, Texas Instruments (TI) TUSB1104, is the optimal part for this application but it is a non-released part as of this writing. It is shown here with permission from TI. The TI TUSB1044 is a similar part that is released and may be used for context but may not be totally suitable here.
A single TX and RX SuperSpeed pair Type-A connector option is implied by some resistor stuffing options in Figure 30 below (R5W6 through R5W9, not populated) but the Type-A connector details are not shown in this Figure set. The Type-A implementation is discussed in Section 3.7.3. above.
This example includes a USB Power Delivery controller, Texas Instruments TPS65994, in Figure 34 below. In this example, the power delivery is out of the COM-HPC Carrier, at 5V and at up to 3A. See Section 3.7.7. above more some discUuSsBs3io.n2 oGnENP2ow#0er(DHeSlIivOe)ry-cHoPnCtroClOleNrNs.ROW C & D Figure 30: USB 3.2 Gen 2x2 Type-C (1 of 6): Option Resistors for Type-C or Type-A

FROM COM-HPC CONN
COM USB0_SSTX0COM USB0_SSTX0+ COM USB0_SSRX0COM USB0_SSRX0+

CAD NOTE:
TRI-PAD OPTION

R5W9 1 0201
0.05W R5W8 1
0201 0.05W R4W15 1
0201 0.05W R4W14 1
0201 0.05W

2 RES
0 0% 2
RES 0 0%
2 RES
0 0% 2
RES 0 0%

USB0_SSTX0_TCPUSB0_SSTX0_TCP+ USB0_SSRX0_TCPUSB0_SSRX0_TCP+

OUT OUT IN IN

COM COM

USB0USB0+

R5W7 R5W6 R4W9 R4W8
CAD NOTE:

1 0201
1 0201
1 0201
1 0201

2 EMPTY
0 20% EMPTY 0 20% EMPTY 0 20% EMPTY 0 0%

H30143-001

TRI-PAD OPTION

R6J10 1 0201
0.05W R6J5 1
0201 0.05W

2 RES
0 0%
2 RES
0 0%

USB0_SSTX0_TYPAUSB0_SSTX0_TYPA+ USB0_SSRX0_TYPAUSB0_SSRX0_TYPA+
USB2_P0_TCPUSB2_P0_TCP+

R6J11 1

2

0201 EMPTY

0 0%

R6J6

1

2

0201 EMPTY 0 0%
H30143-001

USB2_P0_TYPAUSB2_P0_TYPA+

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Reference Schematics and Block Diagrams

Figure 31: USB 3.2 Gen 2x2 Type-C (2 of 6): Port Multiplexer and Redriver

+V3P3_A

IN IN
COM COM COM COM IN IN OUT OUT

USBC0_RDVR_EN BUF_PLT_RST#
USB0_SSTX1+ USB0_SSTX1USB0_SSRX1+ USB0_SSRX1USB0_SSTX0_TCP+ USB0_SSTX0_TCPUSB0_SSRX0_TCP+ USB0_SSRX0_TCP-

R4W54 RES 1 R5W20 RES 1

R5W13 RES R5W12 RES

1 1

C5W3 X5R C5W2 X5R

1 1

R5W10 RES R5W11 RES

1 1

C4W1 X5R C4W2 X5R

1 1

10% 25V

20

0402

20

0402

A93549-001

2 2

0 0

0201 0201

2 2

H30143-001
220NF 0201 220NF 0201

2 2

J95198-001
0 0

0201 0201

2 2

H30143-001
220NF 0201 220NF 0201

J95198-001

+V3P3_A

IN

USBC0_RDVR_FLIP

R4W28 1
0 0%

IN

USBC0_RDVR_SCL

R4W32 1
0 0%

BI USBC0_RDVR_SDA

R4W34 1
0 0%

IN

2
0402 EMPTY
2
0402 RES
2
0402 RES

R5W27 R5J2

1 1K

1 1K

5%

5%

2 EMPTY 2 EMPTY 0402 0402

R4W22 R4W59 R5J1

1 1K 5%

1 1K 5%

1 1K 5%

2 EMPTY 2 EMPTY 2 EMPTY 0402 0402 0402

R5W15 R4W45 R5W24

1 1K

1 1K

1

A93549-016 1K

5%

5%

5%

0.0625W 2 EMPTY 2 EMPTY 2 EMPTY

0402 0402 0402

USBC0_RDVR_A1_SSEQ1

USBC0_RDVR_A0_SSEQ0

USBC0_RDVR_MODE

USBC0_RDVR_CEQ1

USBC0_RDVR_CEQ0

USBC0_RDVR_VIO_SEL

USBC0_RDVR_AEQCFG

USBC0_RDVR_EQCFG

R5W28 R5J5

1 1K 5%

1 1K 5%

2 EMPTY 2 RES 0402 0402

R4W20 R4W61 R5J4

1 1K

1 1K

1 1K

5%

5%

5%

2 EMPTY 2 EMPTY 2 EMPTY 0402 0402 0402

R5W16 R4W42 R5W21

A93549-016

1 1K

1 1K

1 1K

5%

5%

5%

0.0625W 2 EMPTY 2 EMPTY 2 EMPTY

0402 0402 0402

GND

R4W49 A93549-023
10K 1 5%
0.0625W EMPTY 2 0402

USBC0_RDVR_EN_R USBC0_RDVR_SLP_S0#

USB0_SSTX1_TCP_R+ USB0_SSTX1_TCP_R-

USB0_SSRX1_TCP_C+ USB0_SSRX1_TCP_C-

USB0_SSTX0_TCP_R+ USB0_SSTX0_TCP_R-

USB0_SSRX0_TCP_C+ USB0_SSRX0_TCP_C-

IN IN

USBC0_RDVR_A1_SSEQ1 USBC0_RDVR_A0_SSEQ0

IN

USBC0_RDVR_TEST1

IN

USBC0_RDVR_MODE

USBC0_RDVR_SCL_FLIP

USBC0_RDVR_SDA_AEQENZ

IN IN

USBC0_RDVR_CEQ1 USBC0_RDVR_CEQ0

IN

USBC0_RDVR_VIO_SEL

IN

USBC0_RDVR_AEQCFG

IN

USBC0_RDVR_EQCFG

OUT OUT OUT OUT OUT OUT OUT OUT

R5W19 A93549-023 1 10K 5% 0.0625W 2 EMPTY 0402
EU5W2 IC

TUSB1104

26

EN

4

SLP_S0_N

9

SSTX2_DP

10

SSTX2_DN

12 13

SSRX2_DP SSRX2_DN

16 15

SSTX1_DP SSTX1_DN

19

SSRX1_DP

18

SSRX1_DN

2 35

SSEQ1/A1 SSEQ0/A0

27

TEST1

17

MODE

21

FLIP/SCL

22

AEQENZ/SDA

29 38

CEQ1 CEQ0

14

VIO_SEL

23

AEQCFG

3

EQCFG

VCC VCC VCC VCC CTX2_DP CTX2_DN CRX2_DP CRX2_DN CTX1_DP CTX1_DN CRX1_DP CRX1_DN TESTOUT2 TESTOUT1
NC NC NC NC NC
TP_TPD

+V3P3_A

C5W9

A36096-125 1 10UF

20%

10V

1 6

2 X5R 0402

20

28

40

USB0_SSTX1_RDVR+

39

USB0_SSTX1_RDVR-

37

USB0_SSRX1_RDVR+

36

USB0_SSRX1_RDVR-

33

USB0_SSTX0_RDVR+

34

USB0_SSTX0_RDVR-

30

USB0_SSRX0_RDVR+

31

USB0_SSRX0_RDVR-

8 NC_USBC0_RDVR_TESTOUT2 7 NC_USBC0_RDVR_TESTOUT1

5 NC_USBC0_RDVR_5 11 NC_USBC0_RDVR_11 24 NC_USBC0_RDVR_24 25 NC_USBC0_RDVR_25 32 NC_USBC0_RDVR_32 41

M28498-001

GND

+V3P3_A

R4W36 1 1K
5% 2 EMPTY
0402

R4W56

1

A93549-023 10K

5%

0.0625W 2 RES

0402

R4W40

USBC0_RDVR_TEST1 USBC0_RDVR_SDA_AEQENZ

OUT OUT

1 1K 5%
2 EMPTY 0402

CAD NOTE: PLACE RESISTORS THAT CONNECT TO PIN 21/22 CLOSE TO IC

C5W10

1 0.1UF

10%

25V

2

X7R 0402

C4W14 1 0.1UF
10% 25V 2 X7R 0402

C5W4 1 0.1UF
10% 25V 2 X7R 0402

C4W7 A36096-112 1 0.1UF 10% 25V 2 X7R 0402

GND OUT OUT
IN IN
OUT OUT
IN IN

PIN STRAP

MODE = F (I2C MODE) VIO_SEL = F (3.3V I2C)

A1

= F

A0

= 0

I2C ADR = 0X10 (7BIT) AEQENC = SDA AEQCFG = CTRL BY FULLAEQ_UPPER_EQ REGISTER

GND

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USB3.2 GEN2 #0 (HSIO) - HPC CONN ROW C & D
FigFuROrMeR3ED2R:IVERUSB 3.2 Gen 2x2 Type-C (3 of 6): EMI Mitigation and ESD Protection

IN

USB0_SSTX0_RDVR-

IN

USB0_SSTX0_RDVR+

IN

USB0_SSTX1_RDVR+

IN

USB0_SSTX1_RDVR-

R4Y6

1

2

0201 EMPTY 0.05W 0 0%

L4Y3

1

2

J16541-001

CHOKE

4

3 100MA

SM_A 90 30%

R4Y5

1

2

0201 EMPTY H30143-001 0.05W 0 0%

R4Y12

1

2

0201 EMPTY

0.05W 0 0%

L4Y6

1

2

4 SM_A

J16541-001 CHOKE 3 100MA 90 30%

R4Y11

1

2

0201 EMPTY 0.05W 0 0%

H30143-001

USB0_SSTX0_L-

OUT

USB0_SSTX0_L+ USB0_SSTX1_L+

OUT OUT

USB0_SSTX1_L-

OUT

OUT USB0_SSRX0_RDVROUT USB0_SSRX0_RDVR+ OUT USB0_SSRX1_RDVR+ OUT USB0_SSRX1_RDVR-

R4Y18

1

2

0201 EMPTY

0.05W 0 0%

L4Y7

1

2

4 SM_A

J16541-001 CHOKE 3 100MA 90 30%

USB0_SSRX0_L-

IN

R4Y21

1

2

USB0_SSRX0_L+

IN

0201 EMPTY H30143-001

0.05W 0 0%

R4Y8

1

2

0201 EMPTY

0.05W 0 0%

L4Y4

1

2

4 SM_A

J16541-001 CHOKE 3 100MA 90 30%

USB0_SSRX1_L+

IN

R4Y7

1

2

0201 EMPTY H30143-001

USB0_SSRX1_L-

IN

0.05W 0 0%

Reference Schematics and Block Diagrams

USB0_SSRX1_LUSB0_SSRX1_L+
USB0_SSTX1_LUSB0_SSTX1_L+

CAD NOTE:
PLACE ESD CLOSE TO CONNECTOR

2

2

2

CR4Y13

CR4Y12

CR4Y8

20KV ESD SM 1

20KV ESD SM 1

20KV ESD SM 1

2 CR4Y7 K74755-001 PESD3V3Z1BSF 20KV ESD SM
1

GND

USB0_SSRX0_L+ USB0_SSRX0_L-
USB0_SSTX0_L+ USB0_SSTX0_L-

CAD NOTE:
PLACE ESD CLOSE TO CONNECTOR

2 CR4Y6
20KV ESD SM 1

2 CR4Y5
20KV ESD SM 1

2 CR4Y14
20KV ESD SM 1

2 CR4Y16 K74755-001 PESD3V3Z1BSF 20KV ESD SM
1

+V3P3S

GND

COM

USB0_AUX-

COM

USB0_AUX+

C4V10 0.1UF
125V 0402 C4V9 0.1UF 125V 0402

A36096-112 10% EMP2TY A36096-112 10% EMP2TY

USB0_AUX_RUSB0_AUX_R+

DESIGN NOTE: USBC0 REDRIVER NOT SUPPORT DP MODE, AUX PATH DEFAULT DISCONNECTED

BI

USB2_P0_TCP-

R6K6 1 0402 0.0625W

2 A93549-001 EMPTY 0 0%

L6K3 90
0.4A 1

752402-015 25% IND
4

USB2_P0_L-

R4V28

1

A93549-027 100K

5%

2

0.0625W EMPTY

0402

BI

BI

R4V27

1

A93549-027 100K

5%

2

0.0625W EMPTY

0402

GND

BI

BI

USB2_P0_TCP+

2

3

SM

USB2_P0_L+

BI

R6K5

1

2

0402 0.0625W

EMPTY A93549-001 0 0%

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Reference Schematics and Block Diagrams FiguUSrBe33.23:GEUN2SB#03(.2HSGIOe)n-2xH2PCTyCOpNeN-CRO(W4 oC f&6)D: P- oCrAtPPS oArFtTMERuxCH/ORKEe/dErSiDver Coupling Capacitors

IN

USB0_SSTX0_L-

IN

USB0_SSTX0_L+

IN

USB0_SSTX1_L-

IN

USB0_SSTX1_L+

C4Y6 1

2 X5R

0201 10% 25V

220NF

C4Y5 1

2 X5R

0201 10% 25V

220NF

C4Y9 1

2 X5R

0201 10% 25V

220NF

C4Y10 1

2 X5R

0201 10% 25V

J95198-001

220NF

USB0_SSTX0_C-

OUT

USB0_SSTX0_C+

OUT

USB0_SSTX1_C-

OUT

USB0_SSTX1_C+

OUT

OUT USB0_SSRX0_LOUT USB0_SSRX0_L+ OUT USB0_SSRX1_LOUT USB0_SSRX1_L+

RC SHORT PROTECTION

C4Y17 330NF
1 25V 0201 C4Y19 330NF 1 25V 0201 C4Y7 330NF 1 25V 0201 C4Y8 330NF 1 25V 0201

J96611-001 10% X5R 2 J96611-001 10% X5R 2 J96611-001 10% X5R 2 J96611-001 10% X5R 2

USB0_SSRX0_C-

IN

USB0_SSRX0_C+

IN

USB0_SSRX1_C-

IN

USB0_SSRX1_C+

IN

R4Y17 1 220K
1%

R4Y22 1 220K
1%

R4Y14 1 220K
1%

R4Y13 G13778-001 1 220K 1%

2 RES 0201

2 RES 0201

2 RES 0201

2 RES 0201

GND

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Reference Schematics and Block Diagrams

Figure 34: USB 3.2 Gen 2x2 Type-C (5 of 6): Type-C Power Delivery Controller

+V3P3_PD1_LDO

A93549-016

R4V20 1 1K
5% 2 RES
0402

R4V18 1 1K
5% 2 RES
0402

R4V16

1

A93549-023 10K

5%

2 RES 0402

PD1_I2C3_IRQ# PD1_I2C3_SDA PD1_I2C3_SCL

COM USB01_OC#

R4V5 1 0

2 RES

BI PD2_CONN

R4V4 1 0
0%

2 RES 0402

COM COM COM COM COM COM

USB_PD_I2C_CLK USB_PD_I2C_DAT USB_PD_ALERT# SML1_CLK SML1_DAT PMCALERT#

R4V12 R4V10 R4V14 R4V11 R4V15 R4V9

1 1 1

0 0 0

2 2 2

RES RES RES

1 1 1

0 0 0

2 2 2

RES RES RES

0%

0402

A93549-001

DESIGN NOTE:

TARGET I2C SALVES ADDR FROM PD CTRL

USBC0_RDVR = 0X10 (7BIT)

USBC1_RDVR = 0X12 (7BIT)

EEPROM

= 0X50 (7BIT)

OUT OUT OUT OUT
OUT BI
IN IN IN IN IN

OUT BI

USBC0_RDVR_SCL USBC0_RDVR_SDA

R4V26 R4V19

0 0

1 1

2 2

RES RES

0% 0%

PD1_I2C3_SCL PD1_I2C3_SDA

IN BI

OUT BI

USBC1_RDVR_SCL USBC1_RDVR_SDA

R4V23 R4V22

0 0

1 1

2 2

RES RES

0% 0%

J6J1 CON HDR_1X3
1 2 3

PD1_I2C3_SCL PD1_I2C3_SDA

A91829-001 GND

USBC PD CTRL EEPROM PROGRAMMING HEADER

R4W5 5% R4W6 5% R4W7 5%

10K 10K 10K

1 1 1

0402

2 2 2

RES RES RES

PD1_FLASH_A2 PD1_FLASH_A1 PD1_FLASH_A0

A93549-023

PD1_I2C3_SCL

GND

+V3P3_PD1_LDO

PD1_FLASH_WP

+V3P3_PD1_LDO

U4W1 IC
24AA256

C4W10 A36096-143
1UF 10% 25V X5R 0402
GND

3

A2

2

A1

1

A0

6

SCL

7

WP

VCC

8

SDA

5

PD1_I2C3_SDA

VSS

4

R4W46 1 20K
1%

R4W53 1

2

2

EMPTY 0402

0402 10K RES 5%

GND

K67554-001 GND
24AA256 (K67554-001) ADDR = 0X50 (7BIT)

EU4V1 IC

TPS65994

+V3P3_A_SBY
C4V5 G33975-001 1 10UF 20% 25V 2 X5R 0603 GND

+V3P3_A +V3P3_SBY

D71825-002 1 R5V1 2 1%

0.01

0.1W R4V1

0603 RES

1

2

0.01

0603

0.1W 1% EMPTY

+V5_A

+V3P3_A_SBY

PD1_GPIO9 PD1_GPIO8 USB_TCP01_OC# PD1_GPIO6 USBC1_RDVR_FLIP USBC0_RDVR_FLIP PD1_CONN TP_TCP01_LS_EN USBC1_RDVR_EN USBC0_RDVR_EN PD1_EC_I2C_CLK PD1_EC_I2C_DAT PD1_EC_ALERT# PD1_SML1_CLK PD1_SML1_DAT PD1_PMCALERT# PD1_I2C3_SCL PD1_I2C3_SDA PD1_I2C3_IRQ# +VTCPC1_CC2 +VTCPC1_CC1 +VTCPC0_CC2 +VTCPC0_CC1

8 10 27

GPIO9 GPIO8 GPIO7

29

GPIO6

46

GPIO5

2

GPIO4

28

GPIO3

9

GPIO2

38

GPIO1

45

GPIO0

42 40 43

I2C_EC_SCL I2C_EC_SDA I2C_EC_IRQ_N

41

I2C2S_SCL

44

I2C2S_SDA

39

I2C2S_IRQ_N

1

I2C3M_SCL

48 47

I2C3M_SDA I2C3M_IRQ_N

7 6

PB_CC2 PB_CC1

30

PA_CC2

31

PA_CC1

M21651-001

TP_TCP01_LS_EN PD1_GPIO9 PD1_GPIO8 PD1_GPIO6

R4V3

1 1K 5% 0.0625W
2 RES 0402

R4W4 1 1K
5% 0.0625W 2 RES 0402

VIN_3V3
PP5V PP5V PP5V PP5V PP5V PP5V
PB_VBUS PB_VBUS PB_VBUS PB_VBUS
PA_VBUS PA_VBUS PA_VBUS PA_VBUS
ADCIN2 ADCIN1
LDO_1V5 LDO_3V3
PB_GATE_VSYS PB_GATE_VBUS
PA_GATE_VSYS PA_GATE_VBUS
VSYS
GND THPAD

32

C4V19 H14975-001

C4V16 H14975-001

11 12 17 20 25

1 47UF 20% 10V
2 X5R 0805

1 47UF 20% 10V
2 X5R 0805

26

13 +V_TCP_C1_VBUS_CONN 14 15 16 21 +V_TCP_C0_VBUS_CONN 22 23 24

C4V15

1

2

0402 20% 10V 4.7UF X5R

C4V11

1

2

0402 4.7UF

20% 10V X5R

35 PD1_ADCIN2 33 PD1_ADCIN1

C4V14

1

A36096-125 10UF

20%

10V

2

X5R 0402

GND

C4V13

1

A36096-125 10UF

20%

10V

2

X5R 0402

C4V7 A36096-143 1 1UF 10% 25V 2 X5R 0402

GND

+V1P5_PD1_LDO

37 34

4 TP_PD1B_GATE_VSYS 18 TP_PD1B_GATE_VBUS

5 TP_PD1A_GATE_VSYS 19 TP_PD1A_GATE_VBUS

3 PD1_VSYS 36 49
GND

R4V21

1

A93549-001 0

0%

0.0625W 2 RES

0402

GND

+V3P3_PD1_LDO

C4V4

1

A36096-125 10UF

20%

10V

2

X5R 0402

GND

C4V6 A36096-121 1 2.2UF 10% 10V 2 X5R 0402

C4V8

1

A36096-134 4.7UF

2

20% 10V

X5R

0402

GND

+V3P3_PD1_LDO

R4W2 1 1K
5% 0.0625W 2 RES 0402

R4W3 A93549-016 1 1K 5% 0.0625W 2 RES 0402

GND

DESIGN NOTE:
I2C_EC ADDR (7BIT)
PORT 0 0X20 PORT 1 0X24 SINK MODE DISABLED
PD1_ADCIN1 PD1_ADCIN2

R4V8 A93549-001 0 0% 0.0625W RES 0402

R4V7 1 20K
1%

2

EMPTY 0402

R4V2

1

10K 1%

0.0625W

2

EMPTY 0402

R4V6 A93549-001 0 0% 0.0625W RES 0402

GND

>

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Figure 35: USB 3.2 Gen 2x2 Type-C (6 of 6): Type-C Connector and Port Protection

IN IN
BI BI BI BI OUT OUT

+V_TCP_C0_VBUS_CONN

CR5Y2 C

J58608-001

NSR20F30NXT5G

2A

DIO

SM

A

GND

USB0_SSTX0_C+ USB0_SSTX0_C+VTCPC0_CC1_CONN USB2_P0_L+ USB2_P0_LTCP0_SBU1_CONN USB0_SSRX1_CUSB0_SSRX1_C+

GND

DESIGN NOTE: SUPPORT USB MODE ONLY

J5K4 SCON

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12

USB3_C_SHLD_24P_6M

GND_A1

GND_B2

TX1_DP

RX1_DP

TX1_DN

RX1_DN

VBUS_A1

VBUS_B2

CC1

SBU2

D_A_DP

D_B_DN

D_A_DN

D_B_DP

SBU1

CC2

VBUS_A2

VBUS_B1

RX2_DN

TX2_DN

RX2_DP

TX2_DP

GND_A2

GND_B1

B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

MH1 MH2 MH3 MH4 MH5 MH6

MH1 MH2
MH3 MH4
MH5 MH6

J40583-001

C5Y16 1 0.1UF
10% 10V 2 X5R 0402 GND

C5Y17 1 0.1UF
10% 10V 2 X5R 0402 GND

C5Y13 1 0.1UF
10% 10V 2 X5R 0402

C5Y14 A36096-043 1 0.1UF 10% 10V 2 X5R 0402

GND

GND

USB0_SSRX0_C+ USB0_SSRX0_CTCP0_SBU2_CONN USB2_P0_LUSB2_P0_L+ +VTCPC0_CC2_CONN USB0_SSTX1_CUSB0_SSTX1_C+

OUT OUT BI BI BI BI
IN IN

GND

Reference Schematics and Block Diagrams

+V3P3_PD1_LDO

+V3P3_PD1_LDO

TCP0_FLT#

R4V17

BI BI

+VTCPC0_CC2_CONN 0402
+VTCPC0_CC1_CONN

1 01R5V17

2 TCP0_RPD_G2

2RES

0% TCP0_RPD_G1

0402 0

RES 0%

R4V13

1

A93549-027 100K

5%

0.0625W 2 RES

0402

U4V1 IC
TPD6S300

6 RPD_G2 7 RPD_G1

VBIAS 3 VPWR 10 C_SBU1 1 C_SBU2 2

9 FLT_N

C_CC1 4

BI

USB0_AUX_R+

15 SBU1

BI

USB0_AUX_R-

14 SBU2

C_CC2 5 CC1 12 CC2 11

20 D1 19 D2

GND_1 8 GND_2 13

16 NC1

GND_3 18

17 NC2

GND_TPD 21

+VBIAS_TCP0 C4V20 602433-020
1 0.1UF 10% 50V
2 X7R 0603
GND TCP0_SBU1_CONN TCP0_SBU2_CONN +VTCPC0_CC1_CONN +VTCPC0_CC2_CONN +VTCPC0_CC1 +VTCPC0_CC2

C4V12 A36096-088 1 2.2UF 20% 6.3V 2 X5R 0402 GND
BI BI BI BI BI BI

J52027-001

GND

GND

+VTCPC0_CC1_CONN

C4V18 1 220PF
10% 50V 2 X7R 0402
GND

+VTCPC0_CC2_CONN C4V17 1 220PF 10% 50V 2 X7R 0402 A36096-050
GND

BI

TCP0_SBU1_CONN

BI

BI

TCP0_SBU2_CONN

BI

R4V24

R4V25

1 1M 1% 0.0625W
2 EMPTY 0402

1 1M 1% 0.0625W
2 EMPTY 0402 A93548-209

GND

2

SM

DIO

3.5A

ESD131-B1-W0201

J76907-001

CR6K3

1

USB2_P0_L+

BI

USB2_P0_L-

BI

2

SM

DIO

3.5A

ESD131-B1-W0201

J76907-001

CR6K4

1

GND

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Reference Schematics and Block Diagrams
3.7.11. USB4 An example COM-HPC USB4 implementation, that supports all USB modes up to USB4 Gen 3x2 and the USB Type-C Alternate Modes is shown in Figures 36 through 41 below. Of course this support requires that the COM-HPC Module used supports these modes as well. See Table 10 above for a summary of all the USB modes. This example includes a USB Power Delivery controller, Texas Instruments TPS65994, in Figure 40 below. In this example, the power delivery is out of the COM-HPC Carrier, at 5V and at up to 3A. See Section 3.7.7. above more some discussion on Power Delivery controllers. Figure 36: USB4 on COM-HPC USB Port 2 (Fig 1 of 6): COM-HPC Side RX Coupling Caps
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Figure 37: USB4 on COM-HPC USB Port 2 (Fig 2 of 6): Intel JHL8040R Thunderbolt Retimer Part 1

Reference Schematics and Block Diagrams

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Figure 38: USB4 on COM-HPC USB Port 2 (Fig 3 of 6): Intel JHL8040R Thunderbolt Retimer Part 2

Reference Schematics and Block Diagrams

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Figure 39: USB4 on COM-HPC USB Port 2 (Fig 4 of 6): Output Coupling and Protection

Reference Schematics and Block Diagrams

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Figure 40: USB4 on COM-HPC USB Port 2 (Fig 5 of 6): Power Delivery Controller

Reference Schematics and Block Diagrams

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Figure 41: USB4 on COM-HPC USB Port 2 (Fig 6 of 6): Type-C Connector and USB Port Protector

Reference Schematics and Block Diagrams

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3.8.

Boot SPI on Carrier

Reference Schematics and Block Diagrams

The COM-HPC Base Specification V1.0 describes various boot SPI options at some length in Sections 4.3.9 and 4.3.10. The layout topology for the BOOT_SPI bus is given in Section 6.11.1 of the COM-HPC Base Specification V1.0. Please refer to those Base document sections in addition to the materials presented here to get a bigger picture.
Contemporary x86 chipsets typically have a SPI boot bus with three chip-selects: two for up to two SPI Flash devices to hold various pieces of boot firmware including the BIOS, and possibly a backup BIOS, and a 3rd chip-select dedicated to an on-Module TPM. device. The two chip-set chip-selects for boot SPI flash devices can be routed to either two on-Module SPI Flash devices, or to one on-Module SPI Flash and to one Carrier based SPI Flash device. The various possible permutations are selected by a set of three Module strap pins named BSEL0, 1, and 2. See COM-HPC Base Specification V1.0 Section 4.3.10 Table 10 for the decoding of the BSEL[0:2] pins. It is possible to have the entire boot firmware image reside in a Carrier based SPI Flash device. It is also possible of course to have the entire boot image on the module, and it is possible to split the boot image to have some parts on the Module and some on the Carrier. Some Module designs implement multiplexers to allow even more options.
A typical Carrier Boot SPI Flash implementation is shown in Figure 42 below.. Some points about this Figure are given on the following page.

Figure 42: Boot SPI on Carrier (Example 1)

SPI MODE
COM

QSPI MODE
COM

VCC_BOOT_SPI

COM COM

COM COM COM

BOOT_SPI_IO3 BOOT_SPI_IO2
BOOT_SPI_IO1

15 ohm R3
15 ohm R4 15 ohm R5

COM

BOOT_SPI_IO0 15 ohm R6

COM COM

COM COM

BOOT_SPI_CLK BOOT_SPI_CS#

15 ohm R7

COM

BSEL0

COM

BSEL1

COM

BSEL2

Jumper Block

R1 10K R2 10K

C1 100 nF

U1 8 VCC
7 HOLD# / IO3 3 WP# / IO2 2 DO / IO1 5 DI / IO0 6 CLK 1 CS# 4 GND
Winbond W25Q64JV ( 64 Mbit) W25Q128JV (128 Mbit) W25Q256JV (256 Mbit)

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Reference Schematics and Block Diagrams
· Notes on Figure 42 above:
· The Carrier SPI Flash device power is provided by a special COM-HPC Module pin named VCC_BOOT_SPI. This should be the only power source for the Carrier SPI Flash device and any related pull-ups and bypass capacitors., as shown in the Figure.
· The VCC_BOOT_SPI voltage level may be 3.3V or 1.8V.  This is Module vendor specific.  It is not common or expected that a given SPI Flash device will be able to operate at both 3.3V and 1.8V. A few devices might be able to do so.  The SPI Flash devices listed in the Figure above are 3.3V devices, and are not rated at 1.8V.
· The VCC_BOOT_SPI power net may be in the S5 (suspend) or S0 (on) power domains.  This is Module vendor specific.
· QSPI devices from Microchip / SST are shown in the Figure above.  Windbond is a very popular selection for QSPI devices: W25Q16JV is a sample Winbond base part number for their 16 Mbit part. There are 16, 32, 64 and 128 Mbit offerings from Winbond.
· There are many packaging options available from the QSPI vendors  There are package size differences between vendors even for package names that at first glance sound the same (like SOIC8 etc) ... so care must be taken.  The Winbond SOIC8 packages are smaller than the Microchip devices.
· There are register differences between various SPI Flash vendor offerings. The Module firmware / BIOS may not be compatible with some devices. Check with the Module vendor.  Carrier designers should use parts from the same SPI Flash vendor(s) and family as the Module vendor uses.  There may be reasons to use different package types on the Carrier:  The Module vendor likely uses the smallest possible package size.  Carrier designs may want to implement a removable (socketed) SPI Flash device.  Carrier designers may elect to use a SPI package that is easier to rework.
· Contemporary SPI Flash devices may operate in one of several modes:  Traditional SPI mode (noted at left side of Figure 42 above).  This mode has one data line into the SPI device and one out.  QSPI ("Quad SPI") mode:  This mode has 4 bidirectional data lines, offering a higher net data bandwidth.  The SPI Flash devices typically power up in the traditional SPI Flash mode and must be put into the QSPI mode by software.
· The HOLD# and WP# inputs of a traditional SPI device are disabled by pull-ups R1 and R2 in the Figure above. For QSPI mode operation, the PCB trace stubs from the QSPI data lines to these pull-ups should be minimized.  If the SPI device is to immediately be put into QSPI mode, it is likely possible that R1 and R2 can be omitted.
· There are specific routing rules for the BOOT_SPI_xx nets. See Section 4.4. of this document and Section 6.11.1 of the COM-HPC Base Specification V1.0.

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Reference Schematics and Block Diagrams

Removable / Reprogrammable SPI Flash Devices
In some situations it is desirable or even required to have a socketed or removable Boot SPI Flash device. This is the case, for example, in some casino gaming jurisdictions, to allow the BIOS device to be removed and inspected by a regulatory technician. A socketed or removable BIOS can also be useful in product development situations, allowing easy replacement of a corrupted BIOS device. Some possible socket solutions are listed in Table 15 below:

Table 15: Boot SPI Socket Suggestions

Vendor

Vendor P/N

Notes

Enplas Lotes Generic

ACA-SPI-004-K ACA-SPI-006-T01

Enplas offers a variety of sockets that accept several 8 and 16 pin SOIC sizes.
Winbond and other vendors offer some of their SPI Flash devices in a 16 pin SOIC along with a variety of smaller form factors. It may be easier to find a socket for an SOIC16 device. The Carrier Boot SPI Flash device should be from the same flash vendor and family as the part used on the Module. The package details may be different. Should be suitable for the Microchip SST26VFxxxB SOIJ8 parts.
Suitable for Macronix MX77U25650F (32 MB 1.8V QSPI) or MX77L25650F (32 MB 3.3V QSPI) 16 pin 300 mil SOIC parts shown in Figure 43 below.
Other Lotes socket parts may be relevant here. Winbond offers some of their Flash devices in 300 mil DIP format, for which there are many generic sockets.

Some gaming firms design their own removable BIOS assembles. These are sometimes referred to as "cartridges". This allows the use of any SPI Flash device desired, and it can ensure easy removal and replacement of the device..
Some Carrier designers add features that multiplex signals and power to the Carrier SPI Flash device allowing the device to be used as usual in the system or cut the device off from the system and allow the device to be reprogrammed by a cable to an external piece of programming equipment.
An example of such implementations (SPI device in a socket and a multiplexer to allow the SPI flash device to be programmed by an external programming tool) is shown in Figure 43 below. The programming tool in this case is from a company called Dediprog.

PICMG® COM-HPC® Carrier Design Guide

Rev. 2.1 / Aug 10, 2023 84/159

Reference Schematics and Block Diagrams

Figure 43: Boot SPI on Carrier ­ Socketed Flash and Multiplexer to External Programmer

+V5_SBY

DESIGN NOTE:

+VCC_BOOT_SPI

C5B20

1

A36096-112 0.1UF

10%

25V

2

X7R 0402

GND

S G
D

3 1
2

R5B17

1

A93549-023 10K

5%

0.0625W 2 RES

0402

VCC_BOOT_SPI_GATE

+V1P8_A

+VCC_SPI

R4R7
10K 5% EMPTY 0402

Q6B1 MFET D45305-001 FDN339AN SOT23

CAD NOTE:

DO NOT OVERLAP PAD. PLACE 2 RES BRANCH CLOSE TOGETHER & LOW STUB

COM BOOT_SPI_CS# COM BOOT_SPI_IO0 COM BOOT_SPI_IO1 COM BOOT_SPI_IO2 COM BOOT_SPI_IO3 COM BOOT_SPI_CLK

R7E7 1

2

SPI_CS0_R#

OUT

0402LF CHIP 16.90 1%

R3R20 1 0402

2 RES 0 0%

SPI_CS0_TTK#

OUT

R7F1 1

2

SPI_IO0_R

BI

0402LF CHIP 16.90 1%

R3R27 1 0402

2 RES 0 0%

SPI_IO0_TTK

BI

R7E8 1

2

SPI_IO1_R

BI

0402LF CHIP 16.90 1%

R3R31 1

2

SPI_IO1_TTK

BI

0402

RES 0 0%

R7F2 1

2

SPI_IO2_R

BI

0402LF CHIP 16.90 1%

R4R9 1

2

SPI_IO2_TTK

BI

0402

RES 0 0%

R7E6 1

2

SPI_IO3_R

BI

0402LF CHIP 16.90 1%

R4R10 1 0402

2 RES 0 0%

SPI_IO3_TTK

BI

R7E9 1

2

SPI_CLK_R

OUT

0402LF CHIP 16.90 1%

R3R26 1 0402

2 RES 0 0%

SPI_CLK_TTK

OUT

+V3P3_A +VCC_SPI

+V3P3S

R4R8
10K 5% EMPTY 0402
R4R5
10K 5% EMPTY 0402

R4R11
10K 5% EMPTY 0402 SPI_MUX_EN# SPI_MUX_IN
R4R12

R6B11 A93549-016 1 1K 5% 0.0625W 2 RES 0402

10K

5%

RES

+VCC_SPI

0402
R6B4

GND

+V3P3_A

1

A93549-023 10K

5%

R6B8
A93549-023 1 10K

0.0625W 2 RES
0402

5%

0.0625W 2 EMPTY

0402

+VCC_SPI

TTK_PCH_RTC_RST

BI BI OUT OUT IN OUT IN IN IN OUT BI IN IN BI IN

C4R1 A36096-112 0.1UF 10% 25V X7R 0402

CAD NOTE:
PLACE IC NEAR SPI SOCKET EU4R1 IC

GND

IN IN
BI BI BI BI

SPI_CS0_TTK# SPI_CLK_TTK SPI_IO0_TTK SPI_IO1_TTK SPI_IO2_TTK SPI_IO3_TTK

IN

SPI_MUX_EN#

IN

SPI_MUX_IN

5

TS3A27518E

VCC

NC1

23 SPI_MUX_CS0_TTK#

24

NC

NC2 NC3 NC4

22 SPI_MUX_CLK_TTK 20 SPI_MUX_IO0_TTK 18 SPI_MUX_IO1_TTK

1

COM1

NC5 16 SPI_MUX_IO2_TTK

3

COM2

NC6 19 SPI_MUX_IO3_TTK

4

COM3

6

COM4

7

COM5

9

COM6

NO1

8

17

EN_N

NO2 NO3

10 12

NO4 14

21 11

IN1 IN2

NO5 NO6

15 13

2

GND

25

THPAD

USB2_P4_TTK_L+ USB2_P4_TTK_LTTK_PWR_BTN# TTK_UART0_RX TTK_UART0_TX TTK_UART0_CTS# TTK_UART0_RTS# PWRGOOD_TTK TTK_SUS_S3# TTK_SUS_S4# TTK_PCH_RTC_RST TTK_SMB_DAT TTK_SMB_CLK SPI_TPM_GPIO_RST# SPI_MUX_CLK_TTK SPI_MUX_IO3_TTK TTK_PLTRST#
OUT OUT BI BI BI BI

J6B1 SCON HDR_2X25_K29_K30_K31 (BUE)

TTK3 + DEDIPROG PROG CONN

1 3

2 TTK_RST_BTN 4 NC_ECUART_CTS#

OUT

5

6 NC_EC_UART_RTS#

7

8 NC_EC_UART0_RX

9

10 NC_EC_UART_TX

11

12 V3P3_EC_TTK

13 15 17

14 PORT80_SMB_DAT 16 PORT80_SMB_CLK 18

IN IN

19

20 NC_TTK_SUS_S0#

21 23 25 27

22 TTK_I2C0_DAT 24 TTK_I2C0_CLK 26 TTK_SUS_S5# 28 TTK_CATERR#

BI IN IN IN

33

32 SPI_MUX_CS0_TTK# 34 NC_SPI_CS1_TTK#

IN

35

36

37 39 41 43

38 SPI_MUX_IO2_TTK 40 SPI_MUX_IO1_TTK 42 SPI_MUX_IO0_TTK 44

BI BI BI

45

46 TTK_PLT_DET

R6B17 1

47

48

49

50 +VCC_SPI_TTK_R

R6B18 1

K18833-001

GND

GND

+V3P3_A

R6B24 1

2

10K 0402

RES

A93549-023

+VCC_SPI

C6B3

A36096-112

0.1UF

10%

25V

+VCC_SPI

X7R

0402

GND

2 RES 10K 0402 GND

2 EMPTY 0 0402

C6B2 A36096-112 1 0.1UF 10% 25V 2 X7R 0402

COM PLTRST#

R6B3 1 0

2 RES 0402

GND TTK_PLTRST#

OUT

OUT OUT

RST_BTN_FP PWR_BTN_FP

R6B25 R6B16

1 1

0 0

2 2

RES RES

0402 0402

TTK_RST_BTN TTK_PWR_BTN#

IN IN

COM COM COM COM

UART0_TX UART0_RX UART0_RTS# UART0_CTS#

R6B14 R6B15 R6B12 R6B13

1 1 1 1

0 0 0 0

2 2 2 2

RES RES RES RES

0402 0402 0402 0402

TTK_UART0_TX TTK_UART0_RX TTK_UART0_RTS# TTK_UART0_CTS#

OUT IN OUT IN

COM COM OUT COM

SUS_S3# SUS_S4_S5#
RTC_RST_N RTC_RST# GPIO_09

R6B10 R6B20 R6B9

1 1 1

0 0 0

FROM FUSA CONN

R6B7 R6B19

1 1

0 0

2 2 2

RES 0402 EMPTY 0402 RES 0402

TTK_SUS_S3# TTK_SUS_S5# TTK_SUS_S4#

C6B1

1

2 EMPTY

0402 A36096-112

0.1UF

GND

2 2

RES RES

0402 0402

TTK_PCH_RTC_RST TTK_CATERR#

OUT OUT OUT IN OUT

+VCC_SPI

C3R2

1 0.1UF

10%

25V

2

X7R 0402

C3R3

1

A36096-112 0.1UF

10%

25V

2

X7R 0402

GND
BI BI BI BI IN IN

SPI_IO3_R SPI_IO2_R SPI_IO1_R SPI_IO0_R SPI_CLK_R SPI_CS0_R# NC_SPI_16P_RST#

R7E5
1 10K 5% EMPTY
2 0402

R7F3
A93549-023 1 10K
5% EMPTY 2 0402

DESIGN NOTE:
BOM: SPI CHIP MACRONIX
K91180-001 MX77L25650FMI42 (3.3V SOP16) M35512-001 MX77U25650FMI42 (1.8V SOP16)

XU7E1 SKT
SPI_FLASH_16P

BOARD S0 BOARD G3 , TTK POWERED

2

VCC

1

NC0/SIO3

9

WP_N/SIO2

8 15

SO/SIO1 SI/SIO0

16

SCLK

7 3

CS_N RESET_N

NC NC NC

4 13 14

DNU DNU

5 6

DNU DNU

11 12

GND

10

D91187-001 GND
CAD NOTE:

G75680-001 GND

+VCC_SPI

GPIO9 = LVL_SFTED 3.3V CATERR FROM MODULE

COM COM COM COM COM COM

SMB_CLK SMB_DAT I2C0_CLK I2C0_DAT USB_PD_I2C_CLK USB_PD_I2C_DAT

R6B5 R6B6 R6B21 R6B26 R6B22 R6B23

1 1 1 1 1 1

0 0 0 0
0 0

2 2 2 2 2 2

RES RES
RES RES RES RES

0402 0402
0402 0402 0402 0402

TTK_SMB_CLK TTK_SMB_DAT TTK_I2C0_CLK TTK_I2C0_DAT PORT80_SMB_CLK PORT80_SMB_DAT

OUT BI OUT BI OUT BI

COM RSMRST_OUT#

R4R4

1

2

0402 RES 0

R4R2

A93549-023 10K

1

5%

0.0625W EMPTY 2

0402

Q4R1 C81974-001 BSS138LT1G MFET SOT23

RSMRST_OUT_R#

G 1

R4R1 A93549-023 1 10K 5% 0.0625W 2 RES 0402 RSMRST_OUT_R_FET
3
D G
1
S
2

R4R6

1

A93549-023 10K

5%

0.0625W 2 RES

0402 RSMRST_OUT_R_FET2

3

D

Q4R2 C81974-001

BSS138LT1G

MFET S SOT23

2

R4R3

1

2

0402 RES

SPI_MUX_EN# 0

OUT

PLACE SPI SOCKET NEAR HPC CONN

GND

GND

GND

PICMG® COM-HPC® Carrier Board Design Guide Draft

Rev. 2.1 / (c) Copyright 2021, 2022, 2023 PICMG August 15, 2023

85/159

Reference Schematics and Block Diagrams

3.9.

eSPI

The COM-HPC Client and Server pin-outs support an eSPI (Enhanced Serial Peripheral Interface) port. There may be up to two eSPI devices on the Module and up to two eSPI devices on the Carrier. The eSPI interface is promoted as the successor to to the LPC (Low Pin Count) general x86 I/O interface.

The eSPI data and clock signals run at about 50 MHz. The COM-HPC Base Specification Section 6.11.2 recommends a "balanced tree" routing topology. This is also referenced in Section 4.4. of this document.

Figure 44 below illustrates a "generic" eSPI implementation example for one branch of the tree, that might apply to a Carrier Super I/O, FPGA, CPLD, eSPI to LPC bridge, or other eSPI peripheral.

The COM-HPC eSPI interface is a 1.8V level interface that operates in all power states, S5 through S0. The Figure shows some additional signals that are 3.3V level signals, also active in all power domains, that may be needed for some eSPI peripheral implementations.

Some Carrier situations may require legacy Intel LPC (Low Pin Count) compatibility. The Microchip ECE1200 is a suitable eSPI to LPC bridge device that is referenced in some Intel literature for this task.

Microchip is also a popular vendor for Carrier based management micro-controllers with an eSPI interface.

Figure 44: eSPI Generic Interface Example: SIO, FPGA, LPC Bridge, or Other Peripheral eSPI Device

COM COM COM COM COM
COM COM COM COM
COM COM COM COM

1.8V S5 Power Domain Signals to / from COM-HPC

eSPI_IO3 eSPI_IO2 eSPI_IO1 eSPI_IO0
eSPI_CLK

15 ohm R1 15 ohm R2 15 ohm R3 15 ohm R4
15 ohm R5

Series Damping Resistors

eSPI_CS0# eSPI_CS1#
eSPI_ALERT0# eSPI_ALERT1#

0 ohm R6 Open R7
0 ohm R8 Open R9

Opt on Resistors

eSPI_RST#

PLTRST# RSMRST_OUT#

SUS_CLK

3.3V S5 Power Domain Signals from COM-HPC

+1.8V_A

C1 100 nF

VCC_1V8_S5

U1 VCC_3V3_S5

eSPI_IO3 eSPI_IO2 eSPI_IO1 eSPI_IO0 eSPI_CLK
eSPI_CS#
eSPI_ALERT#

eSPI_RESET# RESET# RESUME_RESET_IN# SUS_CLK GND
Super I/O FPGA / CPLD eSPI to LPC Bridge eSPI Peripheral

+3.3V_A C1 100 nF

PICMG® COM-HPC® Carrier Design Guide

Rev. 2.1 / Aug 10, 2023 86/159

3.10.

DisplayPort Over DDI

Reference Schematics and Block Diagrams

Figure 45: DisplayPort Over DDI

R?

0

0603

SHIELD

DDI0_PAIR0+ COM DDI0_PAIR0- COM DDI0_PAIR1+ COM DDI0_PAIR1- COM DDI0_PAIR2+ COM DDI0_PAIR2- COM DDI0_PAIR3+ COM DDI0_PAIR3- COM DDI0_DDC_AUX_SEL COM
DDI0_SDA_AUX+ COM DDI0_SDA_AUX- COM

8x 0402 25V 100n

C310

C311

C312

C313

C314

C315

C316

C317

DP0_CEC

DP0_HPD

DLP11TB800UL2L TR31 DP0_TXP0 DP0_TXN0
DLP11TB800UL2L TR30 DP0_TXP1 DP0_TXN1
DLP11TB800UL2L TR32 DP0_TXP2 DP0_TXN2
DLP11TB800UL2L TR33 DP0_TXP3 DP0_TXN3
DLP11TB800UL2L TR34 DP0_AUXP DP0_AUXN

+3.3V_S F7
NANOSMDC075F
+5V_S R278

2

1

L28

D57

SDM2U40CSP-7B

Q30

2

3

1K 0402

1

SI2312CDS-T1-GE3

BLM18PG121SN1J C319
100n 25V 0402

3.3V_DP0 D58
ESD9X3.3ST5G

G1 CN52 G2

1

2

D0+

3

4

D0-

5

6

GND

7 8

D2+

9

10

D2-

11

12

GND

13

14

CAD/GND

15

16

AUX+

17

18

AUX-

19

20

GND

G3 G4

GND D1+ D1GND D3+ D3CEC/GND GND HPD PWR

W DPE-20F5L1BU3

R200

0 0603

R279

SHIELD

100K 0402

DP0_CEC DP0_HPD DDI0_DDC_AUX_SEL

R275 R276 R277

5.1M 0402 100K 0402 1M 0402

DP0_AUXN

10

DP0_AUXP

9

DP0_HPD

7

DDI0_DDC_AUX_SEL 6

D54 1 2 4 5

DP0_AUXN
DP0_AUXP DP0_HPD DDI0_DDC_AUX_SEL

AOZ8809ADI-05

8

3

DDI0_HPD

COM

U49

6 +3.3V_S

Y1

A1 1

C318

5 VCC GND 2

100n

4 Y2

A2 3

25V 0402

NC7W Z16P6X

DP0_HPD

DP0_TXN1 10 DP0_TXP1 9 DP0_TXN0 7 DP0_TXP0 6 DP0_TXN3 10 DP0_TXP3 9 DP0_TXN2 7 DP0_TXP2 6

3

8

D55 1 2 4 5

DP0_TXN1 DP0_TXP1 DP0_TXN0 DP0_TXP0

AOZ8809ADI-05

D56 1 2 4 5

DP0_TXN3 DP0_TXP3 DP0_TXN2 DP0_TXP2

AOZ8809ADI-05

8

3

PICMG® COM-HPC® Carrier Design Guide

Rev. 2.1 / Aug 10, 2023 87/159

Reference Schematics and Block Diagrams
Notes on DisplayPort over DDI:
· COM-HPC supports three DDI channels, designated DDI0, DDI1 and DDI2. The Figure above uses DDI0 as an example.
· DisplayPort data pairs are capacitively coupled, near the DisplayPort cable connector, as seen in the Figure above (C310 through C317).  This is in contrast to HDMI data pairs which are typically DC coupled.  However, some HDMI buffers / level shifters / redrivers use AC coupling at the buffer inputs and DC coupling at the buffer outputs.
· The DisplayPort AUX channel data pair (net names DDI0_SDA_AUX+ and ­ in this example) are AC coupled on the COM-HPC Module, when the DDI channel is used in DisplayPort mode.  When the DDI channel is used in HDMI mode, the DDIx_SDA_AUX+ and ­ pair (where `x' is 0,1 or 2) are DC coupled on the Module, for the HDMI SDA and SCL I2C setup channel.
· The COM-HPC signal DDIx_DDC_AUX_SEL signals are Module input signals that are used to select either DisplayPort or HDMI mode.  If the signal is pulled or driven low, or left NC, then the Module invokes DisplayPort mode.  If the signal is driven to a logic high, then the Module invokes HDMI mode.  In this schematic example, the DDI0_AUX_SEL Module input signal is pulled low by R277 and ESD protected by part of ESD diode array D54.
· Almost all connections to the DP connector CN52 in the Figure are provided with EMI suppression components (common mode choke elements TR30 through TR34) and ESD protection arrays (D54 through D56).  The EMI and ESD mitigation components used must be appropriate for the high data rates used by the DisplayPort data pairs.  For the ESD diode arrays, this means selecting parts with a sufficiently low pin capacitance.  For the EMI chokes, the selected parts should have a low differential impedance but a relatively high common mode impedance.  It is extremely important that all the nets the DisplayPort data path be routed as differential pairs, preferably against an unbroken GND plane and without any stubs, or with minimal stubs.  Note that the ESD protection arrays used in the example have 2 lands for each net being protected. This is to facilitate no-stub "flow through" routing.  The ESD diode arrays should be positioned next to the DP connector pins.  ESD diode array pins can be pin-swapped if needed to provide a cleaner PCB layout.  DP connector pin 18 is used as a "Hot Plug Detect" signal. The external display drives this signal to a logic high to signal a display hot plug event. This signal is ESD protected by an element of D54 and buffered and level translated by U49 before being passed on to the COM-HPC module. The buffer input is pulled down by R276 in the example, ensuring that the COM-HPC HPD input signal is low if no DP display is present.

PICMG® COM-HPC® Carrier Design Guide

Rev. 2.1 / Aug 10, 2023 88/159

Reference Schematics and Block Diagrams
Some COM-HPC DisplayPort implementations may require a Carrier based redriver. A few industry offerings are listed in Table 16 below. There are of course more parts available on the market.

Table 16: DisplayPort Redrivers and Retimers

Vendor

P/N

Notes

Diodes Inc

PI3DPX1203B PI3DPX8121

Parade Semicon- PS8463 ductor
Texas Instruments DS160PR410

4 lane DisplayPort 1.4 redriver; up to 8.1 Gbps link rate
DisplayPort 1.4 and 2.0 compatible 2:1 mux and redriver, 2 sets of 4 lane inputs and a 4 lane output, with up to a 10 Gbps link rate.
DisplayPort 1.4 redriver (8.1 Gbps) HDMI 2.0 redriver (6 Gbps) 4 lanes
This part is primarily a 4 lane PCIe Gen 4 capable redriver. However, the TI literature states that the part can be used for DisplayPort 2.0 redriver purposes, by setting a certain strap to disable the "PCIe Detect" mode. This is a very high bandwidth part and may work well with all DisplayPort modes.

There are quite a few USB Type-C and a few USB4 port multiplexers that incorporate redriver and in some cases retimer circuits. Such products come from Diodes Inc., Texas Instruments, and others. The Intel JHL8040R, also known as the "Burnside Bridge", does DisplayPort, USB and PCIe retiming along with other USB Type-C and Thunderbolt functions.

PICMG® COM-HPC® Carrier Design Guide

Rev. 2.1 / Aug 10, 2023 89/159

3.11.

HDMI Over DDI

Figure 46: HDMI Over DDI

Reference Schematics and Block Diagrams

R38 0402 R39 0402 R40 0402

I2C addr = 0x70

0ohms 1% 0ohms 1% 0ohms 1%

DDI0_A0 DDI0_A1 DDI0_A4

R41 0402 R42 0402 R43 0402 R46 0402 R47 0402 R48 0402 R49 0402 R50 0402 R51 0402 R52 0402

0ohms 1% 0ohms 1% 0ohms 1% 0ohms 1% 0ohms 1% 0ohms 1% 0ohms 1% 0ohms 1% 0ohms 1% 0ohms 1%

DDI0_PM DDI0_DE0 DDI0_DE1 DDI0_BST0 DDI0_BST1 DDI0_BST2 DDI0_BST3 DDI0_VOD1 DDI0_PS0 DDI0_PS1

GND *HDMI buffer has internal pull ups

COM DDI0_DDC_AUX_SEL

10Kohms 1%

DDI0_A0 DDI0_A1 DDI0_A4

DDI0_PM DDI0_DE0 DDI0_DE1

COM COM COM COM COM COM COM COM
+3.3V_S R57 0402

DDI0_PAIR0+ DDI0_PAIR0-
DDI0_PAIR1+ DDI0_PAIR1-
DDI0_PAIR2+ DDI0_PAIR2-
DDI0_PAIR3+ DDI0_PAIR3-
HDMI_SCL HDMI_SDA DDI0_BST0 DDI0_BST1 DDI0_BST2 DDI0_BST3 DDI0_VOD1 DDI0_PS0 DDI0_PS1

22 16 17 20
NC
21 1 2

U6

A0 A1 A4 PEN PIN_MODE DE1 DE0

V_VDD_3 V_VDD_9 V_VDD_15 V_VDD_24 V_VDD_27 V_VDD_33 V_VDD_36

+3.3V_S_DDI0
3 9 15 24 27 33 36

4 A0RX_+ 5 A0RX_-

A0TX_+ 35 A0TX_- 34

HDMI0_PAIR2+ HDMI0_PAIR2-

7 A1RX_+ 8 A1RX_-

A1TX_+ 32 A1TX_- 31

HDMI0_PAIR1+ HDMI0_PAIR1-

10 A2RX_+ 11 A2RX_-

A2TX_+ 29 A2TX_- 28

HDMI0_PAIR0+ HDMI0_PAIR0-

13 A3RX_+ 14 A3RX_-

A3TX_+ 26 A3TX_- 25

HDMI0_CLK+ HDMI0_CLK-

19 SCL 18 SDA 39 BST0 40 BST1 41 BST2 42 BST3 23 VOD1 37 PS0 38 PS1

GND_6 6 GND_12 12 GND_30 30 THMPAD_43 43
GND

PI3HDX1204-B

HDMI0_PAIR0+ HDMI0_PAIR0-
HDMI0_PAIR1+ HDMI0_PAIR1-

L1

1 IN_1+ 2 IN_1-

OUT_1+ 10 OUT_1- 9

4 IN_2+ 5 IN_2-

OUT_2+ 7 OUT_2- 6

3 GND_3

GND_8 8

EMI8042MUTAG

HDMI0_PAIR2+ HDMI0_PAIR2-

L2

1 IN_1+ 2 IN_1-

OUT_1+ 10 OUT_1- 9

HDMI0_CLK+ HDMI0_CLK-

4 IN_2+ 5 IN_23 GND_3

OUT_2+ 7 OUT_2- 6 GND_8 8

GND

EMI8042MUTAG

GND

HDMI0_SCL

HDMI0_SDA

HDMI0_HPD

HDMI0_DATA0+ HDMI0_DATA0-
HDMI0_DATA1+ HDMI0_DATA1-
HDMI0_DATA2+ HDMI0_DATA2-
HDMI0_DCLK+ HDMI0_DCLK-

J2 7 TMDS_DATA0+ 9 TMDS_DATA08 TMDS_DATA0_SHIELD 4 TMDS_DATA1+ 6 TMDS_DATA15 TMDS_DATA1_SHIELD 1 TMDS_DATA2+ 3 TMDS_DATA22 TMDS_DATA2_SHIELD 10 TMDS_CLOCK+ 12 TMDS_CLOCK11 TMDS_CLOCK_SHIELD

+5.0V_S_DDI0 V_+5V_POWER 18

15 SCL

DDC/HEC/CEC_GND 17

16 SDA

S1 S1

19 HOT_PLUG_DETECT/HEC_DATA+

S2 S2

13
NC

CEC

S3 S3

14
NC

RESERVED/HEC_DATA-

S4 S4

GND

FCI_10029449-001TLF

GND

+5.0V_S 1A1-S

D2

F1 +5.0V_S_FDDI0

2

1

1812

PMEG2010AE

+5.0V_S_DDI0

+3.3V_S

D1

2

1

PMEG2010AE

+3.3V_S_DDI0

C41 0603 C43 0402 C44 0402 C45 0402 C46 0402 C47 0402 C48 0402 C49 0402

C42 0603 C50 0402

10uF 16V
0.1uF 25V
0.1uF 25V
0.1uF 25V
0.1uF 25V
0.1uF 25V
0.1uF 25V
0.1uF 25V

10uF 16V
0.1uF 25V

GND GND
+3.3V_S_DDI0

GND GND GND GND GND GND GND GND
+5.0V_S

*Optional HDMI I2C configuration control

COM COM

+3.3V_S

U7

1 V_VCCA

V_VCCB 8

I2C0_CLK I2C0_DAT

2 A0 3 A1

B0 7 B1 6

25V 0.1uF 1% 2.8Kohms 1% 2.8Kohms

0402 C51 0402 R54 0402 R53

4 BSS138DW
Q1 5
3 D4 2 MMBZ6V8 3
1

COM DDI0_HPD

HDMI_SCL HDMI_SDA

To Buffer

HDMI0_HPD
NC

To connector

GND

5 OE FXMA2102

GND

4
GND
+3.3V_S

+5.0V_S_DDI0

0402 C52 0402 R45 0402 R44

R55

1% DNI 0402

R56

1% DNI 0402

COM COM

DDI0_SCL__AUX+ DDI0_SDA__AUX-

2.8Kohms

2.8Kohms

+3.3V_S

U8

1 V_VCCA

V_VCCB 8

2 A0 3 A1

B0 7 B1 6

5 OE

GND 4

FXMA2102

GND

*Video I2C needs one buffer per port

25V 0.1uF 1% 2.8Kohms 1% 2.8Kohms

2 D3 MMBZ6V8 3
1
HDMI0_SCL HDMI0_SDA

GND

To connector

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Reference Schematics and Block Diagrams
Notes on Figure 46: HDMI Over DDI Above
· COM-HPC DDI signals can generally operate in DP mode or HDMI mode. · COM-HPC input signal DDIx_DDC_AUX_SEL (where x is 0, 1 or 2) selects between DP mode and HDMI
mode.  DDIx_DDC_AUX_SEL left open or pulled low selects DP mode for DDIx.  DDIx_DDC_AUX_SEL pulledor driven high to +3.3V_S selects HDMI mode for DDIx. · DP signals are AC coupled  DP data pairs are AC coupled on the Carrier near the DP connectors, as can be seen in Figure 45: Dis-
playPort Over DDI above.  DP AUX_SEL pairs are AC coupled on the COM-HPC Module (nets DDIx_SDA_AUX+ and ­ in Figure
45). · HDMI signals are generally DC coupled ­ at least from the HDMI / TMDS driver outputs, across the HDMI
cable and on to the HDMI / TMDS receiver. DC coupling is shown for the HDMI / TMDS data pairs and the SDA / SCL setup lines in Figure 46 above. · Figure 46 uses a Diodes Inc / Pericom PI3HDX1204B combination HDMI level translator and redriver (U6 in the Figure).  This part can be configured by resistor straps or over I2C. Both options are shown in the Figure.  Components L1 and L2 are On Semiconductor EMI8042MUT offering combined ESD protection and
EMI suppression.  Note that the +3.3V level DDIx_SDA_AUX+ and ­ HDMI setup signals are translated to a +5V level
with component U8. ESD protection is included for all signals facing the outside world. · There are many alternative HDMI level translators on the market.
 Texas Instruments, Analog Devices, Silicon Labs, Diodes Inc. and others offer HDMI level translators, redrivers and retimers.
 Many devices have built in ESD protection and level translation for the HDMI data pairs and the SDA / SCL setup channel.
 See Texas Instruments TPD12S016 for a basic HDMI level translator with integrated ESD protection.  Some HDMI redrivers / retimers use AC coupling at their inputs, and DC coupling to the cable at their
outputs. See, for example, Texas Instruments TDP158. · There may be licensing fees involved if HDMI implementations are used, and strict rules about logo
use. Check with the HDMI organization (www.hdmi.org).

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Reference Schematics and Block Diagrams

3.12.

eDP

Figure 47: eDP Schematic Example

R290

0 0603

G 1 SHI ELD G2

eDP_BKLT_CTRL COM

U66

+3.3V_S

3 1 6

A B C

VCC Y
GND

5 4 2

BKLT_CTRL

74AUP1T97L6X

C664 100n

R566 100K

25V

0402

0402

eDP_HPD

COM

U52

6 +3.3V_S

Y1

A1 1

C361

5 VCC GND 2

25V 100n

4 Y2

A2 3

0402

NC7W Z16P6X

R291
0402 100K

VDISP_BKLT
eDP_VDD_EN EDPHPD
VDISP_VDD

eDP_AUX- COM eDP_AUX+ COM
eDP_TX0+ COM eDP_TX0- COM
eDP_TX1+ COM eDP_TX1- COM
eDP_TX2+ COM eDP_TX2- COM
eDP_TX3+ COM eDP_TX3- COM

10x 0402 25V 100n

C1654 C1655

EXT_EDP_AUX_DN EXT_EDP_AUX_DP

C1651 C1650

EXT_EDP_TXP0 EXT_EDP_TXN0

C1653 C1652

EXT_EDP_TXP1 EXT_EDP_TXN1

C1657 C1656

EXT_EDP_TXP2 EXT_EDP_TXN2

C1659 C1658

EXT_EDP_TXP3 EXT_EDP_TXN3

DLP11TB800UL2L TR1 DLP11TB800UL2L TR2 DLP11TB800UL2L TR3 DLP11TB800UL2L TR4 DLP11TB800UL2L TR5

EXT_EDP_AUX_DN_Filt EXT_EDP_AUX_DP_Filt
EXT_EDP_TXP0_Filt EXT_EDP_TXN0_Filt
EXT_EDP_TXP1_Filt EXT_EDP_TXN1_Filt
EXT_EDP_TXP2_Filt EXT_EDP_TXN2_Filt
EXT_EDP_TXP3_Filt EXT_EDP_TXN3_Filt

CN42 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

I-PEX 20455-040E

PIN 1

G4 G3 SHI ELD

NOTE: To use with straight eDP cables

R300

0 0603

PANEL BACKLIGHT VOLTAGE SELECTION Set 1-2: 12V Set 2-3: 5V (Default)

+3.3V_A 100n C666

JP12

+12V_S

1

U67 NCP45521IMNTW G-H

0402 25V

VCC 3

2 V_BKLT +5V_S
3
2211S-03G
P12 2228CG

10C06n68 25V 0402

1 9

VIN VIN

2 EN

VOUT VOUT

7 8

BLEED 5

R567 1K
0402

10C06n69 25V 0402

VDISP_BKLT F12 5004V02 miniSMDC150F/24-2 10n C670

4 GND 6 PG/SR

eDP_BKLT_EN COM

R568 100K
0402

C10607n1 25V 0402

VDISP_BKLT

C341 C342

C343

C344

C345

22u 25V 100n 25V 100n 25V 100n 25V 100n 25V

0805 0402

0402

0402

0402

PANEL VDD VOLTAGE SELECTION Set 1-2: 5V Set 2-3: 3.3V (Default)

+3.3V_A 100n C674

JP13

+5V_S

1

U69 NCP45521IMNTW G-H

0402 25V

VCC 3

2 V_VDD +3.3V_S
3
2211S-03G
P13 2228CG

10204C500V6n276

1 9

VIN VIN

2 EN

VOUT VOUT

7 8

BLEED 5

4 GND 6 PG/SR

eDP_VDD_EN COM

R570 100K
0402

eDP_VDD_EN

C10608n0 2054V02

R569 402 0402

10204C500V6n277

VDISP_VDD F13 C1500046nV0728 microSMD150F-2

VDISP_VDD

C346 C347

C350

C348

C349

22u 25V 100n 25V 100n 25V 100n 25V 100n 25V

0805 0402

0402

0402

0402

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Figure 48: eDP Connector Pin Numbering 1
I-PEX 20455-040E Pin Numbering
Cable Entry

Reference Schematics and Block Diagrams 40

40

1

VESA and Display Vendor Pin Numbering

Cable Entry
The connector used for most eDP implementations is the I-PEX 20455-040E or equivalent. There can be some confusion about the pin numbering used in eDP systems. The connector vendor defines pin 1 at the left, as shown in the upper part of Figure 48 above. For reasons perhaps better lost to history, VESA and hence the eDP display vendors put pin 1 at the right side of the connector, as illustrated in the lower portion of the Figure, in spite of the datum mark at the left end of the connector.
The eDP schematic sample in Figure 47 above uses the I-PEX pin numbering (as PCB designers generally prefer to follow the component vendor's data sheet when making up PCB footprints). The net result here is that I-PEX pin 1 needs to map to VESA / Display pin 40, I-PEX pin 2 to VESA / Display pin 39 and so on. This happens with the straight through cable shown in Figure 47 above (which uses the I-PEX pin numbering on both ends of the cable). This cable works between a COM-HPC Carrier and a VESA eDP display (which uses the VESA pin order).
Display cables for eDP typically use micro-coax wiring. The + and ­ conductors of an eDP data pair travel in separate but adjacent coax lines. Hence they are not electromagnetically coupled within the cable assembly, but since each conductor is completely shielded and are equal length, the differential transmission properties are preserved and this works very well even at the highest eDP data rates. The PCB traces on the Carrier and within the display assembly should be edge coupled differential pairs, as per usual.
Additional eDP Example Material An alternative eDP example implementation is presented in Section 6.2. , Appendix B: Alternative eDP Example near the end of this document.

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3.12.1. eDP / DP Conversions to Other Video Formats

Reference Schematics and Block Diagrams

There are a number of video format conversion bridges available from NXP (www.nxp.com), Chrontel (www.chrontel.com) and others. These products allow conversion from eDP or DP to LVDS, analog VGA , HDMI, DVI and a host of older video formats such as CVBS, S-Video, BT656, BT1120, YPbPr etc.
LVDS displays are not directly supported by COM-HPC. However conversion from an eDP or DP source (from COM-HPC) to LVDS input format displays is easily achieved using either the NXP PTN3460 (PTN3460I for the industrial temperature version) or the Chrontel CH7515. All common LVDS formats (single channel, dual channel, 16 / 18 / 24 bit color depths) are supported by these NXP and Chrontel parts.
COM-Express Modules from several vendors routinely use the NXP PTN3460I behind the scenes to produce the COM-Express LVDS outputs from the chipset eDP channel.
It may be wise to check with your Module vendor before selecting an eDP / DP conversion part, as the vendor may have a preference and have software / firmware support favoring a particular part. Some subtleties such as VESA EDID support, backlight control etc. may be easier using the video conversion part(s) supported by the COM-HPC Module vendor.
Analog VGA support is still important in some limited markets. The NXP PTN3355 and the Chrontel CH7517 are popular parts for this task.

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3.13.

MIPI-CSI Camera Interface

Figure 49: MIPI-CSI

CSI0_RX0-

R1 0ohm

CSI0_RX1+ CSI0_CLK-

R2 0ohm R5 0ohm

CSI0_RX2+ CSI0_RX3-

R8 0ohm R9 0ohm

CSI0_RST#_3V CSI0_I2C_CLK_3V
+3.3V_S

R12 0ohm

R13 0Ohm
C1 0.1uF_10V

CN1

FPC/FFC_22

G3

G4

22 21
20 19
18 17
16 15
14 13
12 11
10 9
8 7
6 5
4 3
2 1

G1

G2

Molex/525592253

R3 0ohm R4 0ohm
R6 0ohm R7 0ohm
R10 0ohm R11 0ohm

Reference Schematics and Block Diagrams
CSI0_RX0+ CSI0_RX1CSI0_CLK+ CSI0_RX2CSI0_RX3+ CSI0_ENA_3V CSI0_MCLK_3V CSI0_I2C_DAT_3V

+1.8V_S

+3.3V_S

C4 1uF_6.3V
CSI0_ENA CSI0_RST#

U2 2 VCCA VCCB 19

C5 1uF_6.3V
C2 1uF_6.3V

1 3 4 5 6 7 8 9

A1 A2 A3 A4 A5 A6 A7 A8

B1 B2 B3 B4 B5 B6 B7 B8

20 18 17 16 15 14 13 12

CSI0_ENA_3V CSI0_RST#_3V
CSI0_I2C_CLK CSI0_I2C_DAT

10 OE

GND 11

+3.3V_S

+1.8V_S

+3.3V_S
C3 1uF_6.3V

+3.3V_S

U1

1 2 3 4

VCCA SCLA SDAA GND

VCCB SCLB SDAB
EN

8 7 6 5

TCA9517ADGKR_VSSOP8

R14

2.2K_+-1%

R15

2.2K_+-1%

CSI0_I2C_CLK_3V CSI0_I2C_DAT_3V

TXS0108EPWR_TI

1

5

CSI0_MCLK

3

R16 0ohm NI

Vcc OE

2

4

R1 1k NI

Gnd U3

NI

74LVC1G125_SOT23-5

CSI0_MCLK_3V
R18 0ohm_+-1%

A typical Carrier board MIPI-CSI implementation is shown in Figure 49 above. There is no standard connector for MIPI-CSI use. The Molex part shown in the Figure above is a reasonable choice but many others are used in various situations. The example above distributes +3.3V_S power to the camera, appropriate for many camera assemblies. However, many MIPI cameras are 1.8V devices, and the COM-HPC MIPI-CSI is defined as a 1.8V interface in the COM-HPC Base Specification document.
Camera and support software selection is an important part of implementing a MIPI-CSI system. The cameras have particular data formats and non-linear data compensation requirements to account for camera characteristics. It is important to have a software driver plan that aligns with the camera choice and the Module chipset or SOC choice. There may well be NRE charges from the Module vendor to get a MIPI-CSI camera solution working, unless the vendor has a "canned" solution to offer.

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Reference Schematics and Block Diagrams

3.14. 3.14.1.

Audio Interfaces General Discussion

The COM-HPC Client Module pin-out allows for up to four SoundWire audio ports and one I2S audio port. No audio support at all is offered on the COM-HPC Server Module pin-out. The first two COM-HPC Client Mode SoundWire ports, numbered as 0 and 1, are free and clear and are not shared. Port 0 and Port 1 are two pins each, with CLK and DAT lines. The 3rd and 4th COM-HPC SoundWire ports, numbered as 2 and 3, are pin shared with an I2S audio port.
No Intel HD Audio support at all is offered with COM-HPC revision 1.0. However it is to be offered in COMHPC Base Specification revision 1.1 due to some delays in the industry SoundWire rollout.
SoundWire is expected to be the mainstream x86 system audio interface going forward. I2S audio interfaces are also available on many contemporary x86 chipsets. I2S is the most popular audio interface on ARM designs at the time of this writing. This may shift to SoundWire over time.
3.14.2. MIPI SoundWire Summary

· A 2 wire interface (CLK and DAT) is used.  For most implementations there is a single Master and there may be multiple Slaves  The CLK is an output from the Master  DAT is bidirectional signal, with data to and from Slaves  The Master controls the DAT line direction, per MIPI SoundWire protocol
· The SoundWire CLK and DAT lines may be run at 1.8V or 1.2V (per the MIPI specification)  COM-HPC uses 1.8V SoundWire signaling  This signaling should be available in all system states, S5 through S0
· There may be up to 11 Slave devices on a SoundWire bus  It is more common to have up to 4 Slave devices on a single SoundWire bus  There is a MIPI defined enumeration process to identify the Slaves  It involves a bit of trial and error but in time all Slaves are identified
· Some details on SoundWire clocking and signaling include:  The CLK frequency used is set by the Master, and may be as high as 12.288 MHz  The lowest appropriate frequency is used  DDR (Double Data Rate) signaling is used (meaning that data is clocked on the rising CLK edge and the next bit on the falling CLK edge)  The CLK frequency may be slowed or completely stopped by the Master, as required  These clocking / data features allow lower power operation  SoundWire uses a "modified" NRZI (Non Return to Zero Inverted) protocol on the data line  This allows the enumeration capability and other features described in the MIPI specification  Audio data may be encoded in several formats:  PCM (Pulse Code Modulation) ­ the most common format  PDM (Pulse Density Modulation) ­ has low hardware implementation overhead and is useful for simple devices such as digital microphones  Bulk Mode ­ for large data blocks  Slaves may initiate in-band interrupts and wake events  I2C support for SoundWire devices is generally not needed (unlike for I2S)

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Reference Schematics and Block Diagrams
MIPI Slave devices may be wired together either in daisy-chain fashion or in a branched ­ tree topology, as shown in Figure 50 on the next page. In either case, the SoundWire CLK and DAT lines should be routed together ­ not as a differential pair, but as a signal pair following approximately the same route paths, with approximate length matching all along the paths and for each branch, so that the signal flight time from Master to Slave for both the SoundWire CLK and DAT are about the same. If the balanced tree topology is used, the length of branches of the tree should be about the same.
Chipset design guide examples tend to show a point to point SoundWire implementations with signal integrity measures. These include series damping resistors and snubbing capacitors, as depicted in Figure 51 below, The component values are design and layout dependent and may range from 0 to about 22 ohms for the series resistors and from 0 (i.e. not loaded) to about 22 pf for the capacitors.
The MIPI Master ­ to Slave implementation is straightforward, as it only involves the CLK and DAT lines. There are sure to be many more CODEC or MIPI Slave device implementation details ­ such as filtered analog power supplies, decoupling and other component recommendations, analog layout recommendations etc., not covered here. This information is available from the CODEC and Slave device vendors.

Table 17: SoundWire Audio CODECs

Vendor

Vendor P/N

Notes

Cirrus Logic CS42L42

Realtek

ALC711-VD

SoundWire and I2S Audio CODEC ­ data freely available on the web SoundWire and I2S Audio CODEC ­ data restricted at time of this writing

There are quite a few SoundWire Slave devices available, such as microphones and amplifiers, that are simpler than full CODECs. Vendors include Analog Devices, Maxim Integrated Products, TDK, Texas Instruments and more. From a hardware compatibility view, these low end devices may be tied directly to one of the COMHPC SoundWire ports ­ but be sure to check out the software support situation before putting hardware together.
The reference designs from some x86 SOC and chipset vendors show SoundWire device implementations grouped into functions. For example, the first SOC or chipset SoundWire bus may host two or more output amplifiers, the second SoundWire bus an audio CODEC, and the third Soundwire bus hosts an array of SoundWire microphones.
Check with your COM-HPC Module vendor to see if they have any specific SoundWire device recommendations and port mapping recommendations.

Intel SoundWire Sample Schematics and Design Guide
Sample SoundWire implementations may be found in some Intel reference schematics. See, for example, NDA protected Intel document numbers 627073 and 627205.
Intel NDA protected document number 627205 devotes several pages to SoundWire design They basically show a "balanced tree" with two branches of approximately equal length, and with two SoundWire loads. An alternative daisy chain arrangement with up to four loads is described as well. Also recommended are some optional series damping resistors. In the COM-HPC case, the optional damping resistors would be placed in the SoundWire clock and data lines near the COM-HPC connector.

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Figure 50: MIPI SoundWire Routing Topologies

COM-HPC Connector

SNDW_DMIC_DAT0 SNDW_DMIC_CLK0

Daisy Chain Topology

SNDW_DMIC_DAT1 SNDW_DMIC_CLK1

Balanced Tree Topology

Reference Schematics and Block Diagrams
SoundWire Slave SNDW_DAT SNDW_CLK
SoundWire Slave SNDW_DAT SNDW_CLK SoundWire Slave SNDW_DAT SNDW_CLK SoundWire Slave SNDW_DAT SNDW_CLK
SoundWire Slave SNDW_DAT SNDW_CLK SoundWire Slave SNDW_DAT SNDW_CLK

Figure 51: MIPI SoundWire Point to Point Connection With SI Components
COM-HPC Connector

SoundWire CODEC

SNDW_DMIC_DAT0

C1

R1

SNDW_DAT

R2

C2

SNDW_DMIC_CLK0

C3

R3

SNDW_CLK

R4

C4

MK1 MK3

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Reference Schematics and Block Diagrams
3.14.3. I2S Implementations on COM-HPC
An I2S audio implementation example specifically for COM-HPC is not available at the time of this writing. There are two I2S audio CODEC examples in the SMARC Design Guide that may be useful for reference:
· Cirrus Logic WM8904 Ultra Low Power CODEC · Texas Instruments TLV320AIC3105 Low Power CODEC SMARC defines two I2S ports versus a single I2S port defined for COM-HPC. Apart from that, the definitions are very close:
· 1.8V logic level signaling. · S0 power domain operation. · Same signal definitions (although pin names do not quite match):
 An I2S clock out pin from the Module to a Carrier Slave.  An I2S data out pin defined.  An I2S data in pin defined.  An I2S Left ­ Right audio channel clock output pin defined.  An I2S audio master clock output defined.
I2S implementations generally require a companion I2C interface to setup I2S device registers. This is evident in the SMARC sample drawings. The digital I/O levels for I2S and I2C on an I2S CODEC are generally the same. The COM-HPC I2S interface is a 1.8V interface, and hence the I2C interface used would need to be at 1.8V. The COM-HPC I2C1 interface is defined to be a 1.8V interface; the COM-HPC I2C0 is a 3.3V interface. Of course level translation can be implemented.
Intel NDA protected document 616553, a schematic for an Elkhart Lake validation platform, shows an I2S CODEC implemented in an x86 based system. Elkhart Lake is an Atom class SOC and is not likely to be implemented on COM-HPC. Nonetheless the example may be useful to designers looking to implement I2S audio on a COM-HPC Carrier.
SoundWire does not require a companion I2C interface. Just the SoundWire Clock and Data lines are sufficient for both audio data and SoundWire slave register setup.

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Reference Schematics and Block Diagrams

3.15. 3.15.1.

Asynchronous Serial Port Interfaces COM-HPC UART Interfaces

Two 3.3V logic level asynchronous serial ports, designated UART0 and UART1 are defined by COM-HPC. Each port has TX and RX signals for data use and RTS# and CTS# signals for optional handshake / flow control use. For logic level use, the TX and RX signals are active high and the RTS# and CTS# signals are active low. Some data sheets omit the trailing `#' signal but the logic level handshake signals are active low nonetheless. The idle state, or `mark' state, of the logic level TX line is high, or 3.3V in the COM-HPC case.
These ports may be used directly as logic level asynchronous serial connections between COM-HPC Module and Carrier based devices, or between COM-HPC Module and Carrier based mezzanine devices such as certain Mini-PCIe or M.2 cards. Care has to be taken that the logic I/O levels match up. Note, for example, the (unused) UART connections on the left side of the M.2 E-Key card shown in Figure 14 above. The PCI-SIG M.2 specification defines the E-Key UART pins to be 1.8V signals so some non-inverting level translation would be needed in this case: 3.3V to 1.8V on the TX and RTS# lines leaving the COM-HPC Module, and 1.8V to 3.3V translation for the RX and CTS# lines coming into the COM-HPC Module. Dozens of suitable logic level translation products are available on the market. One such product is the Texas Instruments SN74LV1T125.
For off-board, cabled connections, the logic level UART signals are usually translated into one of three common formats: RS-232, RS-422 or RS-485. RS-232 is a single ended format in which the `mark' or `idle' or `logic 1' state is a negative voltage between -3V and -25V, and the `space' or `logic 0' state is a positive voltage between +3V and +25V. An RS-232 level translation implementation for UART0 and UART1 is shown in Figure 52 below. This example uses a pair of Maxim (Texas Instruments) MAX3243E level translators. These parts have built in capacitor based charge pumps that create RS-232 compliant voltage levels and avoid the need to distribute a negative voltage on the Carrier. Note that the signal polarities are inverted by the device. This particular Maxim device has built-in +/-15 kV air gap and +/-8 kV contact ESD discharge survivability. There are many similar devices from Texas Instruments, Analog Devices / Linear Technology, Diodes Inc. and others. The cable length that can be achieved with RS-232 interfaces depends on the data rate used. Generally, RS-232 cables lengths are limited to about 50 feet or less.
RS-232 signals are most often used with D subminiature DB-9 or DB-25connectors. The RS-232 standard defines DTE (Data Terminal Equipment) and DCE (Data Communications Equipment) connector pin-outs. A DTE chassis connector is a male connector, and a DCE chassis connector is female. The DTE and DCE pinouts are defined such that a straight cable (pin 1 to pin 1, pin 2 to pin2 etc. on the cable) may be used. With the straight cable, the DTE TX pin (or TX# pin if using that notation) lands on the DCE RX(or RX#) pin, and so on.
For longer cable lengths, on the order of 1000 feet or more , differential signaling formats such as RS-422 or RS-485 are often used. These implementations are usually terminated in the twisted pair cable impedance at the receiving endpoints. Many suitable parts are available from Analog Devices / Linear Technology, Texas Instruments and others. These vendors offer very informative Application Notes. They also offer "multi-protocol" devices ­ devices that can handle RS-232, RS-422 and / or RS-485 hardware protocols. Some of these devices have switchable internal cable termination. Some products from these vendors offer galvanic isolation.
The RTS# handshake line is often used in RS-485 implementations as a transceiver enable line. This of course needs appropriate software support.

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Reference Schematics and Block Diagrams Figure 52: UART0 and UART1 RS-232 Level Translated Asynchronous Serial Ports

COM COM
COM COM

0.22uF 16V
1uF 16V
UART0_TX UART0_RTS#
UART0_CTS# UART0_RX
10Kohms 1%
GND

C1 0402 C5 0402
R1 0402

+3.3V_S U1
28 C1+ 24 C1-

1 C2+ 2 C2-

14 T1IN 13 T2IN 12 T3IN

20
NC
19
18
17
NC
16
NC
15
NC

R2OUTB R1OUT R2OUT R3OUT R4OUT R5OUT

21 INVALID# 23 FORCEON 22 FORCEOFF#
MAX3243E

V_VCC 26

V+
V-
T1OUT T2OUT T3OUT

27
3
9 10 11
NC

1uF C6 16V 0402 1uF C7 16V 0402 RS232_TX0# RS232_RTS0

R1IN 4 R2IN 5 R3IN 6 NC R4IN 7 NC R5IN 8 NC

RS232_CTS0 RS232_RX0#

+3.3V_S

C2 0402

0.22uF 16V

GND 25
GND

GND GND

COM COM
COM COM

0.22uF 16V
1uF 16V
UART1_TX UART1_RTS#
UART1_CTS# UART1_RX
10Kohms 1%
GND

C3 0402 C8 0402
R2 0402

+3.3V_S U2
28 C1+ 24 C1-

1 C2+ 2 C2-

14 T1IN 13 T2IN 12 T3IN

20
NC
19
18
17
NC
16
NC
15
NC

R2OUTB R1OUT R2OUT R3OUT R4OUT R5OUT

21 INVALID# 23 FORCEON 22 FORCEOFF#
MAX3243E

V_VCC 26

V+
V-
T1OUT T2OUT T3OUT

27
3
9 10 11
NC

1uF C9 16V 0402 1uF C10 16V 0402 RS232_TX1# RS232_RTS1

R1IN 4 R2IN 5 R3IN 6 NC R4IN 7 NC R5IN 8 NC

RS232_CTS1 RS232_RX1#

+3.3V_S

C4 0402

0.22uF 16V

GND 25
GND

GND GND

J1

1T
NC

P1

2T P2

3T P3

4T
NC

P4

5T P5

6T
NC

P6

7T P7

8T P8

9T
NC

P9

S1 S1T S2 S2T

GND

GND

KYCON_K42X-E9P-P-A4N * T- top pins, B- bot pins

Pinouts of DB9 are configured as DTE ports

J1

1B
NC

P1

2B P2

3B P3

4B
NC

P4

5B P5

6B
NC

P6

7B P7

8B P8

9B
NC

P9

S1 S1B S2 S2B

GND

GND

KYCON_K42X-E9P-P-A4N * T- top pins, B- bot pins

3.15.2. Legacy Compatibility With 16C550 UART Register Set
The I/O mapped UART that was the defacto standard defined at the dawn of the personal computer age is the National Semiconductor (now Texas Instruments) 16550 or 16C550. Many BIOSes support 16C550 operations early in the BIOS boot (before USB devices are enumerated). Console redirect and Port 80 debug codes are often directed to a 16C550 compatible I/O register set. Windows, Linux and other popular operating systems used in embedded system almost universally support the 16C550 UARTs. The COM-HPC Base Specification encourages but does not require 16C550 register compatibility for the UART0 and UART1 ports. Check with your Module vendor.
Once the operating system is running and drivers are loaded, 16C550 compatibility is a non-issue, but for early boot support it is valuable.

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3.15.3. Alternative / Additional Carrier Board UART Implementations If additional or perhaps higher performance UARTs beyond what the COM-HPC Module provides are needed, there are a number of excellent options available. A few of these are summarized in the Table below..

Table 18: Alternative / Additional Carrier Board UART Implementations

Vendor Interface Sample Vendor 16C550

Features / Notes

P/Ns

Compatible ?

FTDI

USB 2.0 FS FT232RUSB

No

Future Technology Devices Inc Web www.FTDIchip.com Several similar parts available Win 10 and Linux drivers

MaxLinear USB 2.0 FS XR21V1410

No

(Exar)

XR21B1420

Web www.maxlinear.com

MaxLinear PCIe x1 XR17V352

Yes

(Exar)

Gen 2

XR17V354

XR17V358

Microchip USB 2.0 FS MCP2220

No

Web www.maxlinear.com Dual, Quad and Octal parts Very deep FIFOs, high bit rates Native Windows and Linux support Vendor drivers also available RS485 support Web www.microchip.com

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3.16.

I2C / I3C Ports

The COM-HPC pin-out definition supports a traditional I2C port, designated I2C0, and a second port designated I2C1, targeting (optional) MIPI I3C use along with with backward compatibility to traditional I2C.The I2C0 port runs at 3.3V and I2C1 at 1.8V. Both are active in suspend and full-on power states.

I2C is an abbreviation for "Inter Integrated Circuit". It was defined by Philips (and later inherited by NXP) as an easy to use two wire method for a Master device to set and read back Slave peripheral IC registers and data values. It uses, in it's basic form, open-drain drivers and passive pull-ups. The current NXP specification document is freely available (see reference in Section 1.9. ) and defines several modes of operation, summarized in the following Table:

Table 19: I2C Operating Modes

I2C Mode
Standard Fast

Operating Frequency 100 KHz 400 KHz

Max Rise Time
1000 nsec 300 nsec

Fast Plus

1 MHz

High Speed 3.4 MHz

120 nsec

Max Bus Capacitance Notes

400 pF 200 pF (passive pull-up) 400 pF (active pull-up) 550 pF (active pull-up)

See NXP UM10204 Section 5.2 3 Mbps throughput Not described in NXP UM10204 Referenced in some literature including Intel

The COM-HPC Base Specification V1.0 document recommends a 2.2K ohm on-Module pull-up on the I2C0 and I2C1 Clock and Data lines. This value is sufficient for all Standard Mode (100 Khz) situations as the RC time constant is 880 nsec (= 2.2K * 400 pF) in the worst case, under 1000 nsec. In most situations, the I2C bus capacitance is much lower than 400 pF:
· Typical IC pin capacitances are 6 to 8 pF · A typical PCB trace capacitance is 4 pF / inch ­ this varies with stackup details · If, for example, there are 10 devices on the bus and there is a 20 inch total trace length, the bus capaci-
tance would be about 160 pF (= 8 pF * 10 + 4 pF / inch * 20 inch) · This rough calculation includes both the Module and Carrier I2C devices and trace lengths, with about 5
inches assumed on the Module.

The 2.2K Module pull-up is not sufficient for the worst case Fast Mode (400 Khz) passive mode bus capacitance of 200 pF. The 2.2K value handles up to about 100 pF of bus capacitance. A 2nd, parallel set of 2.2K pull-ups on the Carrier I2C Clock and Data lines would be advisable if the bus loading is over 100 pF. The Carrier pull-ups can always be left unpopulated if they are not needed.
There are various application notes on this subject available on-line. See, for example, Texas Instruments document SLVA689 titled "I2C Bus Pullup Resistor Calculation".
The Module design may include active circuitry to better support I2C Fast Mode and to support Fast Mode Plus. Check with the Module documentation or with the Module vendor.

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3.16.1. I2C Addressing
I2C uses a 7 bit addressing scheme to differentiate I2C resources. The address lines are designated A6 ... A0, but they are part of an 8 bit frame, in bit positions 7 through 1. Bit position 0 is used in the I2C device address to designate whether the current operation is a Read (a logic `1') or a Write (a logic `0'). Thus I2C addresses can be described in either 7 bit or 8 bit formats. If using the 8 bit format to describe I2C addresses, the R/W bit is always assumed to be `0'. The 8 bit frame is transmitted MS bit first.
The 4 most significant bits in the 7 bit I2C address field are used to define I2C device categories that are fixed by the I2C specification. The 3 least significant bits allow up to 8 devices within an I2C category to be identified by the I2C silicon vendor and / or the user. There are usually pin straps or specific product SKUs that define the 3 bit LS bit addresses.
It is useful to put together a table of I2C devices and addresses used in a design on both the Module and the Carrier, to ensure that there are no conflicts and to provide the information to software engineers. The Module vendor should provide such a list for I2C devices on the Module that are exposed / accessible on the COMHPC I2C0 and I2C1 buses.
Two I2C memory devices for COM-HPC use, at specific I2C0 addresses, are designated in the COM-HPC Base Specification, Version 1.0, Section 5.2 :
· A Module EEPROM device at hexadecimal address 0x50 (7 bit I2C addressing) or 0xA0 (8 bit addressing) · A Carrier EEPROM device at hex address 0x57 (7 bit addressing) or 0xAE (8 bit addressing) The Module and Carrier EEPROM data structures and contents are described in the PICMG documents EeeP for COM-HPC (Embedded EEPROM for COM-HPC) and the PICMG COM-HPC Platform Management Interface Specification.

Figure 53: I2C0 Example: Carrier EEPROM in S5 Power Domain
+3.3V_A

R1 DNI R2 DNI R3 DNI R4 DNI

COM I2C0_CLK

COM

I2C0_DAT

COM

GPIO_00

R9 DNI

+3.3V_A

U2 6 SCL 5 SDA 7 WP

VCC 8

C1 100 nF

3 2

A2 A1

1 A0

GND 4

Microchip / Atmel AT24C32 (32 Kbit) AT24C64 (64 Kbit)

R5 4.7K R6 4.7K R7 4.7K R8 4.7K

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3.16.2. I2C0 Example: Carrier I2C Device in S0 Power Domain
The COM-HPC I2C0 port is a basic 3.3V I2C port active in all power states (S5 through S0). It is a three wire port with CLK, DAT and ALERT# pins. The ALERT# pin, if supported by the COM-HPC Module, can serve as an interrupt input to the Module. An implementation example is given in Figure 54 below. In this example, a temperature sensor that is in the S0 power domain (+3.3V_S power net) is connected to the S5 domain COMHPC Module I2C0 port through isolation FETs T2, T3 and T4. These FETs serve to prevent the S5 power domain I2C0 port from being dragged down when the +3.3V_S power rail is absent. I2C0 bus pull-up resistors to the +3.3V_A (Always on) power rail are on the COM-HPC Module. Secondary pull-ups to the +3.3V_S (Switched) power rail are shown in the Figure below. The ALERT# pin on the IC shown in the Figure is asserted by the LM75B device when a temperature threshold that had been previously set using the I2C0 interface is crossed.
The 5I2C address of the LM75B devic4e is set at 0x90 (8 bit addressing3 ). The lower 3 bits of the LM75B2 I2C address are set by the A2, A1,A0 pin straps. Up to 7 additional devices could be deployed by setting different addresses options on these pin straps.
Figure 54: I2C0 Example: Carrier TemperaItu2reCSenTseormipn eS0rPaotwuerrDeomSaien nsor
+3.3V_S

1

I2C0_DAT COM

T4 2N7002T
3

R542 4k7 0402 2 I2C0_DAT_S0

+3.3V_S

1

I2C0_CLK COM I2C0_ALERT# COM

T2 2N7002T
3

R540 4k7 0402 2 I2C0_CLK_S0

+3.3V_S

1

T3 2N7002T
3

R541 10k0 0402
2 I2C0_ALERT#_S0

U64

1 2 3

SDA SCL OS

5 6 7

A2 A1 A0

VCC 8 GND 4

LM75B I2C addr: 0x90

+3.3V_S C713
100n 0402 25V

3.16.3.

I2C Bus Buffers / Level Translators

There are a number of bus buffers and level translators that target I2C and SMBus situations. Some suggested vendors and parts to consider are listed in Table 20 below. These parts allow for power domain isolation as the I/O pins go into a high impedance mode if one or both of power rails collapse.

Table 20: I2C Bus Buffers / Level Translators / Power Domain Isolation

Vendor

Part

Notes

Texas Instruments On Semiconductor

TCA9517 FXMA2102

An upgrade and replacement for the popular NXP PCA9517

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3.16.4. I2C1 (COM-HPC) and Optional I3C Support
The COM-HPC Base Specification defines a second I2C port, designated I2C1. This port is a 2 wire port (clock and data; no ALERT#) that operates from the 1.8V S5 and S0 power rails. The COM-HPC specification states that this port supports I2C and optionally supports I3C operation.
I3C is mostly backward compatible with I2C but there are some caveats and differences, summarized in the section just below. If the user "just" wants an additional I2C port, than the I2C / I3C differences are not important and the user may proceed with a traditional I2C implementation, bearing in mind the 1.8V operating voltage and the S5 / S0 power domain. If combined I3C / I2C operation is expected, then the material presented just below is important.
MIPI I3C Discussion The MIPI Alliance has defined a significant enhancement to traditional I2C, known as I3C, an acronym for "Improved Inter Integrated Circuit" communication. I3C is significantly faster than I2C, and has some notable feature improvements, summarized below. It is largely, but not completely, backward compatible with I2C, also noted below.
Recall that I2C is a 2 wire interface (with an optional 3rd wire for an ALERT# input) that operates in most cases as a 100 KHz or 400 KHz interface, with some 1 MHz and 3.4 MHz implementations.
I3C enhancements beyond I2C include:
· 12.5 Mbps SDR (Standard Data Rate) operation using a 12.5 MHz clock · 25 Mbps DDR (Double Data Rate) operation (12.5 MHz clock, using rising and falling clock edges) · 33.3 Mbps Ternary Encoding operation (too complicated to explain here; see the MIPI documentation) · Higher bandwidth and lower power operation
 Active pull-ups rather than passive pull-ups increase speed and lower power consumption · In ­ band interrupts (ALERT# pin not needed) ­ 2 wire operation only · Error detection · Error correction, in the Ternary mode · Dynamic addressing · Hot ­ Join operation (devices may be powered down and rejoin at power up; not same as Hot-Plug)
However, there are some issues with complete backward compatibility between I3C and legacy I2C:
· I2C devices on an active I3C bus need "50 nsec spike filters" in series with their Clock and Data pins to prevent the legacy I2C devices from getting confused by some fast short signals ("spikes") present in I3C traffic.  The spike filters can be simple RC circuits (series resistor in front of I2C device pin, capacitor between IC pin and GND).
· I2C clock stretching is not allowed on an I3C bus · I2C bus 10 bit addressing mode is not allowed in I3C Check with your COM-HPC Module vendor for details about their possible I3C support on the COM-HPC I2C1 port.

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3.17.

Port 80h Debug Display Over COM-HPC USB_PD_I2C

Figure 55: Port 80h Debug Display Over COM-HPC USB_PD_I2C

+3.3V_A

C701 100n 0402 25V

DIG2_G DIG2_F
DIG2_E DIG2_D DIG2_A DIG2_B DIG2_C

R533 R516 R519 R521 R523 R525
R527 R529

100k 0402 270R 0402 270R 0402 270R 0402 270R 0402 270R 0402
270R 0402 270R 0402

DIG2_NU DIG2_G_R DIG2_F_R
DIG2_E_R DIG2_D_R DIG2_A_R DIG2_B_R DIG2_C_R

U58

10 11 12 13 14 15 16 17

P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7

+3.3V_A R531 USB_PD_I2C_DAT COM USB_PD_I2C_CLK COM

10k 0402

INT_PCD1#

22 20 19

INT SDA SCL

I2C Pull-Up on COM-HPC module

PCA6416A

25 TP 9 VSS

VDD(P) 21 VDD(I2C) 23

C702 100n 0402 25V

P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7
ADDR
RESET

1 DIG1_NU 2 DIG1_G_R 3 DIG1_F_R 4 DIG1_E_R 5 DIG1_D_R 6 DIG1_A_R 7 DIG1_B_R 8 DIG1_C_R

R534 R518 R520 R522 R524 R526
R528 R530

100k 0402 270R 0402 270R 0402 270R 0402 270R 0402 270R 0402
270R 0402 270R 0402

DIG1_G DIG1_F
DIG1_E DIG1_D DIG1_A DIG1_B DIG1_C

18

+3.3V_A

24 RES_PCD1# R532

10k 0402

8 bit addr: 0x40

DIG2_A DIG2_B DIG2_C DIG2_D DIG2_E DIG2_F DIG2_G
+3.3V_A

MSB

D66

10 9 7 5 4 2 1 6

CA0 CA1

3 8

a b c

a f b
g

d

e f g

e c d

DP

DP

+3.3V_A

7SEG10CAGRN

Kingbright SA39-11GWA

DIG1_A DIG1_B DIG1_C DIG1_D DIG1_E DIG1_F DIG1_G
+3.3V_A

LSB

D67

10 9 7 5 4 2 1 6

CA0 CA1

3 8

a b c

a f b
g

d

e f g

e c d

DP

DP

+3.3V_A

7SEG10CAGRN

The COM-HPC hardware specification allows for BIOS Port 80h debug codes to be serialized and transmitted over the USB Power Delivery I2C bus (COM-HPC pins USB_PD_I2C_DAT and _CLK). Figure 55 above illustrates how the codes can be de-serialized and displayed on a pair of 7-segment LED displays. This feature is optional.
There are other methods for Port 80h codes to be conveyed for debug use. The Port 80h I/O writes can be picked off of the eSPI bus or even a PCIe x1 link by appropriate hardware such as a CPLD, FPGA or some Super I/O devices. Some BIOSes provide 4 digit codes as opposed to 2 digit codes.
It is also possible for special debug versions of a BIOS to transmit ASCII versions of the Port 80h debug codes over one of the asynchronous serial ports ... check with your Module vendor.

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3.18.

Carrier BMC with IPMB Link to Module

A high end Carrier BMC (Board Management Controller) using an Aspeed AST2500 / AST2520 is shown in Figures 56, 57 and 58 below. The three Figures do not show the complete implementation ­ the DDR4 memory devices and the Aspeed power section are omitted. What is shown are the features relevant to COM-HPC operation ­ the interfaces to the COM-HPC and to the user. Refer to the Aspeed documentation for complete design information.

The BMC interfaces to the Module include IPMB, eSPI, UART1, I2C0 and a collection of status and control signals such as power state status, reset, power button etc. BMC operator interfaces include a USB port for keyboard and mouse use, a VGA port, and a 1000BASE-T management network interface.

The primary management interface to the COM-HPC Module is over the IPMB. The Module, if it supports management functions, includes a small satellite controller known as the MMC (Module Management Controller). The MMC has at minimum an IPMB slave interface to the BMC.

The design shown includes two SPI Flash devices attached to the BMC, and an eSPI interface to the COMHPC. The COM-HPC BIOS image can reside in the BMC attached SPI Flash. This allows the BMC to manage Out of Band Flash BIOS updates, if so desired.

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5 Figure 56: Carrier BMC with IPM4 B Link to Module ­ Sheet 1 3

2

U5A

R45 DNI X_100K_+-1%

PLTRST# COM R44

0ohm_+-5% PCIE_BMC_RSTN L20 PERST

AST2500/2520 Rev.1.5

PETXP PETXN

For DDR4 Memory

PCIe_REFCLK0_LO+ COM PCIe_REFCLK0_LO- COM
PCIe_BMC_TX+ COM PCIe_BMC_TX- COM

V_M_BMC_DDR4_DQ0 V_M_BMC_DDR4_DQ1 V_M_BMC_DDR4_DQ2 V_M_BMC_DDR4_DQ3 V_M_BMC_DDR4_DQ4
V_M_BMC_DDR4_DQ5 V_M_BMC_DDR4_DQ6 V_M_BMC_DDR4_DQ7 V_M_BMC_DDR4_DQ8 V_M_BMC_DDR4_DQ9
V_M_BMC_DDR4_DQ10 V_M_BMC_DDR4_DQ11 V_M_BMC_DDR4_DQ12 V_M_BMC_DDR4_DQ13 V_M_BMC_DDR4_DQ14
V_M_BMC_DDR4_DQ15

V_M_BMC_DDR4_DQS0_DP V_M_BMC_DDR4_DQS1_DP V_M_BMC_DDR4_DQS0_DN V_M_BMC_DDR4_DQS1_DN

V_M_BMC_DDR4_RST_N

V_M_BMC_DDR4_ALERT_N

+1.2V_A

+0.6V_A

C6

K21 K22 M21 M22
U10 W10 Y10 AA10
U9 Y9 W9 V9 AA8 Y8 Y7 W8 AA6 W7 V7 U7
AB9 AB7 AB10 AB6
AB17 U16
R3512 DNI 4.7K_+-1% T9
0.1uF_25V

eSPI_CLK COM eSPI_CS0# COM eSPI_CS1# COM eSPI_ALERT0# CO M eSPI_ALERT1# CO M eSPI_RST# C O M

R70 R72 R74 R76 R78
R80

+3.3V_A

R68

240ohm_+-1% W11

0ohm_+-5%

0ohm_+-5%

C22

DNI 0ohm_+-5%

F21

0ohm_+-5%

F22

DNI 0ohm_+-5%

G22

0ohm_+-5%

J20

H21

R81

10K_+-1% LPC_PME_N H22

H20

C12 A12 B12
D9 D10 E12 C11 B11

F19 E21 F20 D20 D21 E20 G18 C21

B14 D14 D13 E13

PEREFCLKP PEREFCLKN PERXP PERXN

PCI-Express

PEREXT

MDQ0 MDQ1 MDQ2 MDQ3 MDQ4 MDQ5 MDQ6 MDQ7 MDQ8 MDQ9 MDQ10 MDQ11 MDQ12 MDQ13 MDQ14 MDQ15 MDQS0 MDQS1 MDQS0 MDQS1 MRESET MALERT MVREF
MIOZ

DDR3/DDR4

MCK MCK MCKE MODT MCS MRAS MCAS MWE MBA0 MBA1 MBA2_MBG0 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14_MACT MA15 MDM0 MDM1

GPIOAC4_ESPICK_LCLK GPIOAC5_ESPICS_LFRAME GPIOAC6_ESPIALT_LSIRQ GPIOAC7_ESPIRST_LPCRST

LPC ESPI

GPIOAC0_ESPID0_LAD0 GPIOAC1_ESPID1_LAD1 GPIOAC2_ESPID2_LAD2 GPIOAC3_ESPID3_LAD3

GPIOB4_USBCKI GPIOB5_LPCPD_LPCSMI GPIOB6_LPCPME GPIOB7

GPIOB0 GPIOB1 GPIOB2 GPIOB3

GPIOC0_SD1CLK_SCL10 GPIOC1_SD1CMD_SDA10 GPIOC2_SD1DAT0_SCL11 GPIOC3_SD1DAT1_SDA11 GPIOC4_SD1DAT2_SCL12 GPIOC5_SD1DAT3_SDA12 GPIOC6_SD1CD_SCL13 GPIOC7_SD1WP_SDA13

GPIOY4_SCL1 GPIOY5_SDA1 GPIOY6_SCL2 GPIOY7_SDA2 GPIOQ0_SCL3 GPIOQ1_SDA3 GPIOQ2_SCL4 GPIOQ3_SDA4

SD/SDIO I2 C

GPIOD0_SD2CLK GPIOD1_SD2CMD GPIOD2_SD2DAT0 GPIOD3_SD2DAT1 GPIOD4_SD2DAT2 GPIOD5_SD2DAT3 GPIOD6_SD2CD GPIOD7_SD2WP

GPIOK0_SCL5 GPIOK1_SDA5 GPIOK2_SCL6 GPIOK3_SDA6 GPIOK4_SCL7 GPIOK5_SDA7 GPIOK6_SCL8 GPIOK7_SDA8 GPIOA4_TIMER5_SCL9 GPIOA5_TIMER6_SDA9

GPIOA0_MAC1LINK GPIOA1_MAC2LINK GPIOA2_TIMER3_SPI1CS1 GPIOA3_TIMER4

GPIO

GPIOQ4_SCL14 GPIOQ5_SDA14 GPIOQ6_OSCCLK GPIOQ7_PEWAKE

1 OF 4

AST2500A2-GP

L21 PCIE_BMC_RX_P_C L22 PCIE_BMC_RX_N_C

C4

0.1uF_25V

C5

0.1uF_25V

K20 PD_P2E_BMC_PEREXT R47

200ohm_+-1%

COM PCIe_BMC_RX+ COM PCIe_BMC_RX-

AB11 AB12 Y11 V11 AA12 W12 AB13 Y12 U12 Y13 W13 V13 AB14 W14 U14 W15 V15 AB16 AA16 W16 Y16 U13 AA14 Y14 AB15 Y15 U15 U8 AB8
G21 G20 D22 E22
K19 L19 L18 K18

V_M_BMC_DDR4_CLK_DP V_M_BMC_DDR4_CLK_DN V_M_BMC_DDR4_CKE V_M_BMC_DDR4_ODT V_M_BMC_DDR4_CS_N
V_M_BMC_DDR4_MA16 V_M_BMC_DDR4_MA15 V_M_BMC_DDR4_MA14 V_M_BMC_DDR4_BA0 V_M_BMC_DDR4_BA1
V_M_BMC_DDR4_BG0 V_M_BMC_DDR4_MA0 V_M_BMC_DDR4_MA1 V_M_BMC_DDR4_MA2 V_M_BMC_DDR4_MA3
V_M_BMC_DDR4_MA4 V_M_BMC_DDR4_MA5 V_M_BMC_DDR4_MA6 V_M_BMC_DDR4_MA7 V_M_BMC_DDR4_MA8 V_M_BMC_DDR4_MA9 V_M_BMC_DDR4_MA10 V_M_BMC_DDR4_MA11 V_M_BMC_DDR4_MA12 V_M_BMC_DDR4_MA13
V_M_BMC_DDR4_ACT_N

For DDR4 Memory

V_M_BMC_DDR4_DM0 V_M_BMC_DDR4_DM1

R73 R75 R77 R79

0ohm_+-5% 0ohm_+-5% 0ohm_+-5% 0ohm_+-5%

COM COM COM COM

eSPI_IO0 eSPI_IO1 eSPI_IO2 eSPI_IO3

eSPI

BMC_SCL1 BMC_SDA1
BMC_SCL3 BMC_SDA3
BMC_SCL8 BMC_SDA8

M18 BMC_SCL1

R82

M19 BMC_SDA1 R83

M20

P20

A11 BMC_SCL3

R86

A10 BMC_SDA3 R87

A9

B9

0ohm_+-5% 0ohm_+-5%

COM COM

I2C0_CLK I2C0_DAT

0ohm_+-5% 0ohm_+-5%

COM COM

IPMB_CLK IPMB_DAT

I2C0 IPMB

L3

L4

L1

N2

N1

P1

P2

BMC_SCL8

R96

R1

BMC_SDA8 R97

C14

A13

0ohm_+-5% 0ohm_+-5%

SENSOR_SCL SENSOR_SDA

For Thermal Sensor

N21

N22

B10

N20

R3516 DNI 0ohm_+-5% R3515 DNI X_4.7K_+-1%

COM WAKE0#
+3.3V_A

5

4

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1 +3.3V_A
R48 DNI X_4.7K_+-1% R49 DNI X_4.7K_+-1% R52 DNI 4.7K_+-1% R53 DNI 4.7K_+-1% R62 DNI X_4.7K_+-1% R63 DNI X_4.7K_+-1%
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Reference Schematics and Block Diagrams

5

4

3

2

1

Figure 57: Carrier BMC with IPMB Link to Module ­ Sheet 2

+3.3V_A

+3.3V_A

+3.3V_A

EEPROM_0

+3.3V_A

D

BMC_SPICK

R102 R105

BMC_SPIMOSI R106

BMC_SPIMISO R108

+3.3V_A

R110 R111

4.7K_+-1% BMC_SPICS0

7

22ohm_+-1% BMC_SPICK1_R 16

22ohm_+-1% BMC_SPI1_MOSI_R15

22ohm_+-1% BMC_SPI1_MISO_R 8

4.7K_+-1% 4.7K_+-1%

BMC_SPI1_WP_N 9 BMC_SPI1_HOLD_N 1

CS SCLK SI/SIO0 SO/SIO1/PO7 WP/SIO2 HOLD/IO3

VCC 2

PO0 PO1 PO2 PO3 PO4 PO5 PO6

6 5 4 11 12 13 14

3 NC

GND 10

SPI-FLASH-SKT_16

C7 0.1uF_25V

BMC_SPICK

R103 R107

BMC_SPIMOSI R104

BMC_SPIMISO R109

+3.3V_A

R112 R114

4.7K_+-1% 22ohm_+-1%
22ohm_+-1%
22ohm_+-1%
4.7K_+-1% 4.7K_+-1%

BMC_SPICS1 BMC_SPICK2_R

EEPROM_1

7 16

CS SCLK

BMC_SPI2_MOSI_R15 SI/SIO0

BMC_SPI2_MISO_R 8 SO/SIO1/PO7

BMC_SPI2_WP_N 9 BMC_SPI2_HOLD_N 1

WP/SIO2 HOLD/IO3

VCC 2

PO0 PO1 PO2 PO3 PO4 PO5 PO6

6 5 4 11 12 13 14

3 NC

GND 10

C8 0.1uF_25V

D

SSKT_LOTES_ACA-SPI-006-K01

SPI-FLASH-SKT_16

SSKT_LOTES_ACA-SPI-006-K01

U5B

BMC_SPICS0 BMC_SPICS1

R118 R117

22ohm_+-1% BMC_SPICS0_R 22ohm_+-1% BMC_SPICS1_R

AB19 AA19
T19

CARRIER_HOT# COM

R124

T17 22ohm_+-1% Y19
W19 V19

FWSPICS0 GPIOR0_FWSPICS1 GPIOR1_FWSPICS2 GPIOR2_SPI2CS0 GPIOR3_SPI2CK GPIOR4_SPI2MOSI GPIOR5_SPI2MISO

AST2500/2520 Rev.1.5
BMC SPI
SPI2 ACPI

FWSPICK FWSPIMOSI FWSPIMISO GPIOY0_SIOS3 GPIOY1_SIOS5 GPIOY2_SIOPWREQ GPIOY3_SIOONCTRL

AA18 BMC_SPICK U17 BMC_SPIMOSI T18 BMC_SPIMISO R22 FM_SLPS3_N R21 FM_SLPS5_N P22 P21

R1002 R122

CARRIER_HOT#

0ohm_+-5% 0ohm_+-5%

COM COM

SUS_S3# SUS_S4_S5#

CARRIER_HOT#

+3.3V_A

R120 DNI 4.7K_+-1% R123 DNI X_10K_+-1%

R129 DNI 4.7K_+-1%

+3.3V_S

C

R3549
0ohm_+-5%C2783 0.1uF_25V DNI

RST_BTN

1

3

2

4

SW-TACT-TS-A02

+3.3V_A

+3.3V_A +3.3V_A
C110 0.1uF_25V

5

N19 T21 T22 R20
V20 U19 R18 P18 R19 W20 U20 AA20
T2 T1 U1 U2 P4 P3 V1 W1

Digital Video O utput
GPIOAB0_VPODE_NOROE GPIOAB1_VPOHS_NORWE GPIOAB2_VPOVS_WDTRST1 GPIOAB3_VPOCLK_WDTRST2 GPIOS0_VPOB2_SPI2CS1 GPIOS1_VPOB3_BMCINT GPIOS2_VPOB4_SALT5 GPIOS3_VPOB5_SALT6 GPIOS4_VPOB6 GPIOS5_VPOB7 GPIOS6_VPOB8 GPIOS7_VPOB9 GPIOL0_NCTS1 GPIOL1_NDCD1_VPIDE GPIOL2_NDSR1 GPIOL3_NRI1_VPIHS GPIOL4_NDTR1_VPIVS GPIOL5_NRTS1_VPICLK GPIOL6_TXD1 GPIOL7_RXD1

GPIOZ0_VPOG2_NORA0_SIOPBI GPIOZ1_VPOG3_NORA1_SIOPWRGD
GPIOZ2_VPOG4_NORA2_SIOPBO GPIOZ3_VPOG5_NORA3_SIOSCI
GPIOZ4_VPOG6_NORA4 GPIOZ5_VPOG7_NORA5 GPIOZ6_VPOG8_NORA6 GPIOZ7_VPOG9_NORA7 GPIOAA0_VPOR2_NORD0_SALT7 GPIOAA1_VPOR3_NORD1_SALT8 GPIOAA2_VPOR4_NORD2_SALT9 GPIOAA3_VPOR5_NORD3_SALT10 GPIOAA4_VPOR6_NORD4_SALT11 GPIOAA5_VPOR7_NORD5_SALT12 GPIOAA6_VPOR8_NORD6_SALT13 GPIOAA7_VPOR9_NORD7_SALT14
GPIOM0_NCTS2_VPIB2 GPIOM1_NDCD2_VPIB3 GPIOM2_NDSR2_VPIB4
GPIOM3_NRI2_VPIB5 GPIOM4_NDTR2_VPIB6 GPIOM5_NRTS2_VPIB7
GPIOM6_TXD2_VPIB8 GPIOM7_RXD2_VPIB9

Y20 AB20 AB21 AA21 U21 W22 V22 W21
Y21 V21 Y22 AA22 U22 T20 N18 P19
Y1 AB2 AA1 Y2 AA2 P5 R5 T5

+3.3V_A +3.3V_A

4.7K_+-1% R3547

5

FM_BMC_PWRBTN_OUT_N

Vcc 1

U14A Gnd SN74LVC2G07DBVR_SOT23-6

2

R131

0ohm_+-5%

R132 R133 R134

0ohm_+-5% 0ohm_+-5% 0ohm_+-5%

UART1
COM UART1_CTS# COM UART1_RTS# COM UART1_RX COM UART1_TX

+3.3V_A C

4.7K_+-1% R3546

6

R3548

COM PWRBTN#

0ohm_+-5%

PWR_BTN

3

1

4

2

SW-TACT-TS-A02

R3550 0ohm_+-5% C2782
0.1uF_25V DNI

R377 4.7K_+-1%

R378 4.7K_+-1%

RSTBTN# COM
B

R379 0ohm_+-5%

4

2

Vcc 3

RST_BMC_SYSRST_BTN_OUT_N

Gnd U14B SN74LVC2G07DBVR_SOT23-6

B20 C20 F18 F17 E18 D19 A20 B19

GPIOE0_NCTS3 GPIOE1_NDCD3 GPIOE2_NDSR3 GPIOE3_NRI3 GPIOE4_NDTR3 GPIOE5_NRTS3 GPIOE6_TXD3 GPIOE7_RXD3

GPIOF0_NCTS4_LHAD0 GPIOF1_NDCD4_LHAD1 GPIOF2_NDSR4_LHAD2
GPIOF3_NRI4_LHAD3 GPIOF4_NDTR4_LHCLK GPIOF5_NRTS4_LHFRAME GPIOF6_TXD4_LHSIRQ
GPIOF7_RXD4_LHRST

J19 J18 B22 B21 A21 H19 G17 H18

B

For BMC Console Port

BMC_UART_TXD5 BMC_UART_RXD5

K1 K2

TXD5 RXD5

BMC/System U ART

GPIOH0_NCTS6 GPIOH1_NDCD6 GPIOH2_NDSR6
GPIOH3_NRI6 GPIOH4_NDTR6 GPIOH5_NRTS6
GPIOH6_TXD6 GPIOH7_RXD6

A18 B18 D17 C17 A17 B17 A16 D18

For Management

A

BMC_RMII1_50M_CLK
BMC_RMII1_RXD0 BMC_RMII1_RXD1 BMC_RMII1_CRS_DV

R150 R151 R152 R153
R154

DNI X_10K_+-1% DNI X_10K_+-1% DNI X_10K_+-1% DNI X_10K_+-1%
DNI X_10K_+-1%

R136 R137 R138 R139 R140

0ohm_+-5% RMII1_REF_CLK B4

10K_+-1%

A4

0ohm_+-5% RMII1_RXD0 A3

0ohm_+-5% RMII1_RXD1 D6

0ohm_+-5% RMII1_CRSDV C5

RMII1_RXER C4

RGMII1RXCK_RMII1RCLKI_GPIOU4 RGMII1TXCK_RMII1RCLKO_GPIOT0

RGMII1RXCTL_GPIOU5

RGMII1TXCTL_RMII1TXEN_GPIOT1

RGMII1RXD0_RMII1RXD0_GPIOU6

RGMII1TXD0_RMII1TXD0_GPIOT2

RGMII1RXD1_RMII1RXD1_GPIOU7

RGMII1TXD1_RMII1TXD1_GPIOT3

RGMII1RXD2_RMII1CRSDV_GPIOV0

RGMII1TXD2_GPIOT4

RGMII1RXD3_RMII1RXER_GPIOV1

RGMII1TXD3_GPIOT5

MAC1

GPIOR6_MDC1 GPIOR7_MDIO1

B5 E9 F9 A5 E7 D7 D8 E10

RMII1_REF_CLK RMII1_RXD0 RMII1_RXD1
RMII1_CRSDV RMII1_RXER

C2 C1 C3 D1 D2 E6
D3

RGMII2RXCK_RMII2RCLKI_GPIOV2 RGMII2TXCK_RMII2RCLKO_GPIOT6

RGMII2RXCTL_GPIOV3

RGMII2TXCTL_RMII2TXEN_GPIOT7

RGMII2RXD0_RMII2RXD0_GPIOV4

RGMII2TXD0_RMII2TXD0_GPIOU0

RGMII2RXD1_RMII2RXD1_GPIOV5

RGMII2TXD1_RMII2TXD1_GPIOU1

RGMII2RXD2_RMII2CRSDV_GPIOV6

RGMII2TXD2_GPIOU2

RGMII2RXD3_RMII2RXER_GPIOV7

RGMII2TXD3_GPIOU3

RGMIICK

MAC2

GPIOA6_TIMER7_MDC2 GPIOA7_TIMER8_MDIO2

B2 B1 A2 B3 D5 D4 C13 B13

+3.3V_A

Network BMC_RMII1_TX_EN BMC_RMII1_TXD0
BMC_RMII1_TXD1

L1 120_100MHz_2A

C9 0.1uF_25V

C10 0.1uF_25V

OSC1

4 1

VCC ST

OUT GND

3 2

CLK_50M

50MHz_15pF SG210-50M-STF-L-4085

R145

+3.3V_A DNI

33ohm_+-1% BMC_RMII1_50M_CLK

A

AST2500A2-GP

2 OF 4

R149 X_10K_+-1%

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Reference Schematics and Block Diagrams

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4

3

2

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Figure 58: Carrier BMC with IPMB Link to Module ­ Sheet 3

+3.3V_A

OSC2

D

C12 0.1uF_25V

DNI R161

4 1

VCC ST

OUT GND

3BMC_24M

2

R160

X_10K_+-1% 24MHz_15pF

22ohm_+-1%

EPSON-SG210STF-24M-L

BMC_24M_R

U5C

AST2500/2520

D

C

+3.3V_A

W18

BMC_SRST_BTM_N 0ohm_+-5% R165

+3.3V_A

4.7K_+-1% R169

BMC_SYS_RESET_N U18

BMC_EXT_RST

V18

BMC_HB

BMC_HB_LED

Y18

A

K

Y LG-170Y-CT

R174 330ohm_+-1%

R170 PD_BMC_ENTEST K3

10K_+-1%

BMC_FAN_TACH0

U5 U4

For FAN connector

V5 AB4 AB3

Y4

AA4

W4

V4

W5

AA5

AB5

Y6

ADC Power

Y5 W6

Monitor

V6

CLKIN

Rev.1.5

SRST EXTRST

MISC DAC

HBLED

ENTEST

GPIOO0_TACH0_VPIG8 GPIOO1_TACH1_VPIG9 GPIOO2_TACH2 GPIOO3_TACH3 GPIOO4_TACH4_VPIR2 GPIOO5_TACH5_VPIR3 GPIOO6_TACH6_VPIR4 GPIOO7_TACH7_VPIR5 GPIOP0_TACH8_VPIR6 GPIOP1_TACH9_VPIR7 GPIOP2_TACH10_VPIR8 GPIOP3_TACH11_VPIR9 GPIOP4_TACH12 GPIOP5_TACH13 GPIOP6_TACH14 GPIOP7_TACH15

FAN

DACB DACG DACR
GPIOJ4_VGAHS GPIOJ5_VGAVS GPIOJ6_DDCCLK GPIOJ7_DDCDAT
GPION0_PWM0 GPION1_PWM1 GPION2_PWM2_VPIG2 GPION3_PWM3_VPIG3 GPION4_PWM4_VPIG4 GPION5_PWM5_VPIG5 GPION6_PWM6_VPIG6 GPION7_PWM7_VPIG7

J2 J3 J4
N5 R4 R3 T3
V2 W2 V3 U3 W3 AA3 Y3 T4

VGA_BLU
VGA_GRN VGA_RED

For VGA connector

VGA_HSYNC VGA_VSYNC
VGA_I2C_CLK VGA_I2C_DAT

BMC_FAN_PWM0 For FAN connector

P3V3_BMC_USB2AV33_AUX

FB1

120_100MHz_2A

C14

0.01uF_50V C15

4.7uF_6.3V

+3.3V_A BLM18PG121SN1D

C

B

+2 .5 V _A

C16 1.43K_+-1%
1K_+-1%

0.1uF_25V R193
R198

For BMC Reset

+3.3V_A

+3.3V_A

+1.15V_A
R168 3.3K_+-1%
1

R163 10K_+-1%

5

Vcc NC 2

1

4 BMC_SRST_BTM_N

3

Gnd

U7 74AHC1G14_SOT23-5

3

B C Q2

E PMBT3904_200mA/40V

2

C13 1uF_16V

R171 10K_+-1%

BMC_ADC0 F4 F5 E2 E1 F3 E3 G5 G4 F2 G3 G2 F1 H5 G1 H3 H4
AA17 AB18
E11 D12
C8 C10
C9 D11

ADC0_GPIW0 ADC1_GPIW1 ADC2_GPIW2 ADC3_GPIW3 ADC4_GPIW4 ADC5_GPIW5 ADC6_GPIW6 ADC7_GPIW7 ADC8_GPIX0 ADC9_GPIX1 ADC10_GPIX2 ADC11_GPIX3 ADC12_GPIX4 ADC13_GPIX5 ADC14_GPIX6 ADC15_GPIX7
PECIVDD PECI
NTRST TDI TMS TCK RTCK TDO

ADC
PECI JTAG

USB

USB2AV33 C7

C17

USB2AVRES USB2BVRES

B8 B7

PD_BMC_USB2A_VREF R175 PD_BMC_USB2B_VREF R176

33pF_50V
8.2K_+-1% 8.2K_+-1%

USB2A_DP USB2A_DN

A7 A8

USB2B_DP USB2B_DN

B6 A6

R3536 R3537

0ohm_+-5% 0ohm_+-5%

COM USB3+ COM USB3-

For BMC KVM Keyboard/Mouse

SGPIO

GPIOJ0_SGPMCK GPIOJ1_SGPMLD
GPIOJ2_SGPMO GPIOJ3_SGPMI GPIOG0_SGPS1CK GPIOG1_SGPS1LD GPIOG2_SGPS1I0 GPIOG3_SGPS1I1 GPIOG4_SGPS2CK_SALT1 GPIOG5_SGPS2LD_SALT2 GPIOG6_SGPS2I0_SALT3 GPIOG7_SGPS2I1_SALT4

R2

L2

N3

N4

COM

A19 E19 C19 BMC_THRMTRIP-L E16

VIN_PWR_OK

E17 CNBMC_I2C0_ALERT-L D16 D15 E14

R186

0ohm_+-5% COM

I2C0_ALERT#

+3.3V_A

R1013 4.7K_+-1%

3

Q53 D BSS138LT1_200mA/50V
S +3.3V

G 1

COM PLTRST#

B

2

R166
0ohm_+-5% C2784
0.1uF_25V DNI

BMC_BTN

1

3

2

4

SW-TACT-TS-A02

C18 E15 B16 C16

GPIOI0_SYSCS GPIOI1_SYSCK GPIOI2_SYSMOSI GPIOI3_SYSMISO

AST2500A2-GP

System S PI

GPIOI4_SPI1CS0_VBCS GPIOI5_SPI1CK_VBCK
GPIOI6_SPI1MOSI_VBMOSI GPIOI7_SPI1MISO_VBMISO

B15 C15 A14 A15

3 OF 4

System BIOS

R188

22ohm_+-1%

BMC_SPI1_CS0_N

BMC_SPI1_CLK

BMC_SPI1_MOSI

BMC_SPI1_MISO

For System BIOS Flash

4.7K_+-1%

R126

X_10K_+-1% DNI R127

COM THERMTRIP#

A

A

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Reference Schematics and Block Diagrams

3.19.

General Purpose SPI

The COM-HPC General Purpose SPI port is, from a hardware view, an easy to use interface for Carrier peripherals that requires only four signal pins on the peripheral device (data in, data out, clock and chip select), plus an optional interrupt output. It may be used to implement a wide variety of low to medium speed (circa 4 to 20 MHz signaling rate) peripheral devices such as A/D and D/A converters, touch controllers, CPLDs, FPGAs, Flash memories and many more. The GP SPI interface is significantly faster than traditional I2C ports (400 KHz max for most I2C implementations) but much slower than PCI Express (2.5 GHz signaling and up). A SPI interface is easier to implement within a peripheral device than PCIe, resulting in lower costs.

The COM-HPC pinout definitions allow for four General Purpose SPI chip selects, allowing up to four Carrier GP SPI devices. The COM-HPC GP SPI interface uses 3.3V signal levels, active in the S0 (full on) power state. Carrier GP SPI devices may be daisy-chained or routed in a branch topology with the root at the COMHPC connector. The data in, data out and clock lines for a particular target device on the Carrier should be loosely kept together and have approximately the same length from the COM-HPC connector to the particular target device. The chip-select lines should be routed directly from the COM-HPC connector to the target device.

3.20.

Rapid Shutdown

Rapid Shutdown is a rarely used feature but one that is important to some defense industry segment customers. It's purpose is to rapidly collapse all Module and Carrier power rails and remove all bias voltages to prevent damage to the electronics in certain extreme wartime situations. It is purely a hardware feature, without any consideration for an orderly software shutdown.

It is expected that some COM-HPC Module designs will incorporate Rapid Shutdown capability, but that the feature be depopulated unless needed by certain customers. The feature is both fairly simple in concept but potentially tricky in implementation: if the Module Rapid Shutdown pin is asserted by a 5V logic level signal, all power Module and Carrier rails are collapsed by a N-channel FET and appropriately sized drain resistor on each power rail. The +12V or Wide Range power source to the system must be immediately cut as well, and isolated from any bulk capacitance that might provide hold-up power. This usually is achieved by using hotswap controller devices to gate the system power input, with the bulk hold-up capacitance located at the input side of the hot-swap controller circuitry. All power rails on the Carrier must be collapsed as well.

Design drawings are not shown here. If your Module vendor supports Rapid Shutdown, then they should be able to provide implementation design support.

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Reference Schematics and Block Diagrams

3.21.

Thermal Protection

COM-HPC defines two pins related to thermal protection of the system:

· CARRIER_HOT#  This is a 3.3V level S0 power domain input signal, with an on-Module pull-up  This signal may be left open, or it may be driven low by Carrier hardware if a system over-temperature situation is detected.  Module support for this signal is required, per the COM-HPC Base Specification.  There is no definition in the COM-HPC Base Specification as to how long CARRIER_HOT# should stay low in an system over-temperature situation
· THERMTRIP#  This is a 3.3V level S0 power domain output  If driven low, it indicates that the CPU is in an over-temperature situation  There is no definition in the COM-HPC Base Specification as to how long THERMTRIP# should stay low in an over-temperature situation  Carriers may leave this signal open, or they may act on it  Ideally, a Carrier circuit removes system S0 power if the situation persists and is not a short term glitch, and sets a bit in a non-volatile memory that can be read by Module firmware on the next S0 power up.  A Carrier BMC may also track / process this COM-HPC output signal

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3.22.

System Management Bus (SMBus)

Reference Schematics and Block Diagrams

SMBus Introduction
The SMBus is primarily used to manage system peripherals on the COM-HPC Module and on the Carrier. SMBus devices such as the Serial Presence Detect (SPD) EEPROM(s) for the system RAM, thermal sensors, PCIe devices, clock buffers, Smart Battery, etc. are managed over the SMBus. Designers need to take note of several implementation issues to ensure reliable SMBus interface operation. The SMBus is derived from I2C. However, I2C devices have the potential to lock up the data line while sending information and require a power cycle to clear the fault condition. SMBus devices contain a timeout to monitor for and correct this condition. Designers are urged to use SMBus devices when possible over standard I2C devices. COM-HPC Modules are required to power SMBus devices from the suspend power rail in order to have control in all system power states.
The COM-HPC Module may not function correctly or at all if Carrier SMBus devices interfere with proper Module SMBus device operation.

SMBus Power Domain Isolation
The devices on the Carrier Board using the SMBus are usually powered by the main 3.3V (S0) power rail. To avoid current leakage between the suspend (S5) and the main (S0) power rails, the SMBus devices in the S5 power domain must be separated by a bus switch from S0 domain SMBus devices. FET devices, as shown in Figure 54 above, or I2C / SMBus isolation devices, as shown in Table 20 above may be used to achieve the S5 / S0 power domain isolation.

SMBus Addresses
Since the SMBus is used by the Module and Carrier, care must be taken to ensure that Carrier based devices do not overlap the address space of Module based devices. Typical Module SMBus devices and their binary I2C / SMBus addresses include memory SPD (Serial Presence Detect) addresses 1010 000x, 1010 001x, up to 1010 111x for 8 DIMMs, programmable clock synthesizers (1101 001x), clock buffers (1101 110x), thermal sensors (1001 000x), and management controllers (vendor defined address). The `x' in the binary addresses is the SMBus / I2C R/W bit. Contact your Module vendor for information on the SMBus addresses used on the Module.

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3.23.

General Purpose Inputs / Outputs

Reference Schematics and Block Diagrams

COM-HPC defines 12 General Purpose I/O pins. It is expected that the 12 pins can be individually configured as either inputs or outputs, that they be configured as inputs on power up, that they be powered by the Module 3.3V suspend (S5) power rail, that there be a 100K pull-up on the Module, and that the Module GPIO pins be able to generate interrupts to the Module CPU.
As the COM-HPC GPIO may be inputs, outputs or bidirectional signals, there are a variety of ways to use and protect them. If the target I/O devices are in a different power domain from (I.e targets are in the S0 domain), that needs to be taken into account by an appropriate logic buffer or FET arrangement, similar to the S5 ­ S0 power domain isolation shown in this document for I2C and the SMBus.
If any of the GPIO signals are exposed to the outside world and exposed to human contact and ESD events, then there needs to be appropriate ESD protection, EMI mitigation, and hardening against accidents such as short circuiting or exposure to power rails. The details of the protection implemented depend on the factors such as:
· What level of ESD protection is expected ? · What is the GPIO signal bandwidth ?
 Low bandwidth GPIO signals may be protected with simple measures including:  Dual Schottky diodes: · 1st diode with anode (A) at GND and cathode (K) at the GPIO signal level · 2nd diode with anode at GPIO signal level and cathode at the GPIO VCC level  Alternatives to the dual Schottky diodes proposed above may be specialty diodes or diode arrays designed for ESD mitigation such as those shown in the NBASE-T, Ethernet, USB, DP and HDMI sections of this document.  A series resistor between the Schottky diode K ­ A node and the COM-HPC GPIO pin-out  Possibly a ferrite in between the COM-HPC GPIO pin and the external connector
 If the GPIO signal bandwidth is somewhat higher, then adjustments have to be made:  The ESD diode pin capacitance needs to be lower, and appropriately sized for the bandwidth at hand  The series resistor value needs to be lowered  The ferrite inductance value may need adjustment
· If user abuse is expected (hot plugging, sudden removal etc) then protection measures may include:  Some or all of the protection measures listed just above  Robust buffer ICs that stand between the COM-HPC pins and the protection measures  If the GPIO is to be used as a single direction input or output, then robust buffering is easy  Many bidirectional buffers are available, including buffers that auto-sense the signal direction

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Reference Schematics and Block Diagrams

3.24.

Module Type Detection and Protection

There are three TYPE pins defined in the COM-HPC pin-outs allowing up to eight Types to be defined. At present, three Types are defined, per Table 21 below:

Table 21: COM-HPC Type Definitions

Module Connections

Ref TYPE2

TYPE1

7

NC

NC

6

NC

NC

5

NC

GND

4

NC

GND

3

GND

NC

2

GND

NC

1

GND

GND

0

GND

GND

TYPE0 NC GND NC GND NC GND NC GND

Meaning
Reserved Reserved Reserved Server Module ­ Fixed 12V input Reserved Reserved Client Module - Wide Range 8V to 20V input Client Module ­ Fixed 12V input

COM-HPC Carrier hardware may optionally implement hardware to hold off the application of power to the main Carrier circuits and to the Module if the Module and Carrier Types do not match up. The COM-HPC Client and Server pin-outs are different (the differences are noted in Table 2 earlier in this document) and it is not desirable to power up a system in which the Carrier and Module Types do not match.
The Carrier hardware shown in Figure 59 below holds off power distribution if the Module Type is not a fixed input voltage Client or a wide-range input Client. The example uses and ATX style power supply. The 5V Standby power to the Carrier and Module is cut off by power switch U60 in the Figure. The open drain FET T1 along with pull-down resistor R539 ensure that the ATX power control line (ATX_PSON#) is floating and not pulled low. This prevents the main ATX power rails from coming on. FET T1 should not be replaced by a logic gate as the gate's internal ESD protection diodes might provide a path for the ATX_PSON# signal to be pulled low unintentionally.

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Reference Schematics and Block Diagrams

Figure 59: Module TTyyppeeDeDteecttieocnt/ iPorontecLtioogni­cATX Power Supply and Client Type Module / Carrier
C

+5V_SBY_ATX

VCC_5V_SBY

R534 100k 0402

R535 100k 0402

C703 100n 0402 25V

C704 1u0 0603 16V

U60

1 2

VIN VOUT VIN VOUT

8 7

C706 22u 1206 16V

TYPE2 COM TYPE1 COM
TYPE0 not evaluated. Carrier with ATX PSU supports 'Fixed 12V' and 'Wide Range' Modules

U59

1

5 VCC

2

3

4

GND

SN74LVC1G02

SBY_EN_LSW

4 VBIAS CT 6

SBY_LSW_CT

9 PAD

3 ON
R536 100k 0402

GND 5 TPS22975

C705

4n7 0402 25V

Rise time ~8ms

B

ATX_PSON#

5

4

3

2

3

Example: Server Carrier with AT PSU 12V Runtime Voltage (+VCSCUS__ISN3#) COM no Standby Voltage
D

1
R539 100k 0402

2

T1 2N7002A

1 A
D

4

3

2

1

The Carrier hardware shown in Figure 60 below holds off power distribution if the Module Type is not a Server Type Module. The example uses and AT style supply.

Type Detection Logic

C

Figure 60: Module Type Detection / Protection ­ AT Power Supply and Server Type Module / Carrier

C

+VCC_IN

U62 1 IN

C707 1u0 0805 25V

3 EN

+3.3V_initial

OUT 5 NC 4 LDK320M33R

C708 1u0 0402 10V

2 GND

B

+3.3V_initial

R534 100k 0402

R535 100k 0402

C703 100n 0402 25V

+VCC_IN

TYPE1 COM TYPE0 COM
A TYPE2 COM

+3.3V_initial

U59

1

5 VCC

2

3

4

GND

SN74LVC1G02

R537 100k 0402

C709 100n 0402 25V

U61

1 2A 3B
GND

5
VCC
4
Y

NC7SZ08

C712 22u 1206 25V +3.3V_initial

LSW_EN R538 100k 0402

C710 1u0 0402 10V

LSW_EN

U63

12 13

VIN VIN

10 VCC

11 1 5

EN NC1 NC5

NCP45750

B

VCC to COM-HPC module

Vout Vout Vout

2 3 4

OCP PG SR
VSS

9 8 7 6

SR_VCC A
C711 100n 0402 25V rise time ~12ms

5

4

3

2

1

Server Modules may use either AT or ATX or other style power supplies. An AT supply is used here just as an example.

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4.

PCB Design Rule Summaries

PCB Design Rule Summaries

4.1.

High Speed PCB Design Information ­ Design Guides and Books

4.1.1.

Intel and AMD Design Guides

Intel and AMD have a wealth of design guide material available, although most current materials are NDA (Non Disclosure Agreement) protected and Carrier designers must obtain their own NDAs with these vendors to access these documents.
A few useful documents are listed in Table 22 below. Although these guides are centered around CPU board development there is also much general high speed design information, often in graphical format, about topics such as how to keep differential pairs length matched, about stackups, about via stubs, about voiding planes under certain components and features, and so on. There is also information about peripheral interfaces such as PCIe, USB 3 and 4 etc.

Table 22: Intel and AMD Design Guides Vendor Doc # Description / Title

Notes

AMD Intel
Intel Intel Intel
Intel

5515 576513
607872 618429 627205
406926

Socket SP3 Processor Mother Board DG

Some general high speed PCB design info Fiber weave effect information PCIe Gen 3 and 4 information

Intel Confidential

Some general high speed PCB design info PCB differential pair length matching techniques PCIe Gen 3 and 4 information USB 3.1 Ethernet KR 10G/25G information

Tiger Lake UP3 UP4 Platform DG Fiber weave effect information PCIe Gen 3 and 4 length matching information USB4 routing information

Tiger Lake H Platform DG

Intel Confidential

Fiber weave effect information No stub routing techniques Voiding advice PCIe Gen 4 and Gen 5 advice

Fiberweave Effect White Paper

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PCB Design Rule Summaries

4.1.2.

Books on High Speed PCB Design Principles

The publications listed below are much more academic than the design guides listed in Section Error: Reference source not found above. These books may be useful to designers interested in the engineering and physics details of what is going on with very fast signal propagation.
The book titled High Speed Digital Design: Design Of High Speed Interconnects And Signaling is the newest and perhaps most relevant book in this list. It was written by a trio of Intel engineers and covers contemporary high speed serial interface topics quite thoroughly.

· Advanced Signal Integrity For High-Speed Digital Designs Stephen H.; Heck and Howard L Hall ISBN 13: 9780470192351 ISBN 10: 0470192356 © 2009 Wiley-IEEE Press
· High Speed Digital Design: Design Of High Speed Interconnects And Signaling Hanqiao Zhang, Steven Krooswyk and Jeffrey Ou © 2015 Morgan Kaufman, Elsevier Inc. ISBN: 978-0-12-418663-7
· High-Speed Signal Propagation - Advanced Black Magic Howard Johnson and Martin Graham © 2003 Pearson Education, Prentice Hall Professional Technical Reference
· Right the First Time - A Practical Handbook on High Speed PCB and System Design Volumes 1 and 2 Lee W. Ritchey ©2006 Speeding Edge
· Signal Integrity Issues and Printed Circuit Board Design Douglas Brooks ©2003 Pearson Education, Prentice Hall Professional Technical Reference

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PCB Design Rule Summaries

4.2.

High Speed Serial Interfaces ­ General PCB Design Rules

Figure 61: PCB Cross Section Terms and Notations
Diff Pair - Surface
Plane

Microstrip

Symmetric Stripline

WS W

H2

Asymmetric Stripline

T

D

D

H1 or H

Diff Pair

DX Other Periodic Signal

Dual Stripline or
Dual Asymmetric Stripline

Some of the terms and notations in the Figure above are used in the Tables and text on the following pages. The long copper colored thin rectangles represent the GND or PWR planes and the smaller rectangles, for the most part, the edge coupled differential pairs. The upper and lower signal layers within a Dual Stripline structure should be routed orthogonally to each other to minimize coupling and thereby crosstalk.

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PCB Design Rule Summaries
Table 23: General Design Rules for High Speed Serial interfaces
Ref Rule / Recommendation 1 High speed pairs should be routed as edge-coupled differential pairs referenced to and closely coupled to an un-
broken GND plane. 2 High speed pairs with Nyquist frequencies at 4 GHz or more (PCIe Gen 3,4,5, USB 3.2 Gen2, USB4 Gen 3, Dis-
playPort, eDP, HDMI, Ethernet KR) require the most PCB routing care. 3 The preferred routing environments for high speed pairs are ranked here, from most desirable to least:
1. Symmetric Stripline routing with clean GND planes above and below gives the best signal integrity, but it is often an impractical luxury. The two GND planes should be periodically tied together with stitching vias, every inch or so in both X and Y.
2. Asymmetric Stripline routing with the differential pair traces close the primary reference plane, an unbroken GND plane, and further from the secondary plane. The secondary plane can be a GND plane (preferred) or a power plane, possibly with plane splits.
3. Asymmetric Dual Stripline routing with high speed pairs close to the primary reference plane, a GND plane. The traces on the "other" routing layer should be as far away as possible and be routed orthogonally to the GND referenced high speed pairs. The "other" traces can be high speed pairs as well, if their primary reference plane is also GND and if the two signal layers are orthogonal. If the routes on the Asymmetric Dual Stripline routing layers are not be truly orthogonal (90 degrees) they should be angled at at least 30 degrees relative to each other.
4. Microstrip routing. 4 Use as few vias as possible. What few vias there are should be symmetrically placed, such that the + and ­ lines
in the pair "see" the same obstacles and impedance discontinuities. If there is a reference plane change, there must be a stitching via close to the signal via. If the planes are at the same potential (e.g. both GND), direct (DC coupled) stitching vias are used. If the reference planes are at different potentials (not desirable for high speed pairs) then a stitching capacitor is used near the signal vias. These concepts are illustrated in some of the Design Guides referenced in Table 22 above. 5 The higher speed interfaces may need no-stub vias or very short stub vias. This may mean backdrilling the vias with controlled depth drills to hollow out the unused portion of the via barrel. Alternatively, via structures that are built up or are laser drilled and only transit a limited number of layers (say from Layer 1 to Layer 3, with Layer 2 being a GND plane) may be used. Another strategy to avoid via stubs is to arrange that the vias connect layers on opposite sides of the PCB. Then there is no stub (for outer layer to outer layer) or perhaps a shorter stub. Yet another strategy is to use sequential lamination PCB construction. For example, a 12 layer PCB can be built as two 6 layer PCBs and then laminated together to form a 12 layer PCB, with short vias spanning layers1-6 and layers 7-12 and longer vias spanning layers 1-12. 6 If layer transitions must be done, having the high speed signals in question straddle a common GND plane is beneficial as there is no change in the reference layer. For example, if signal pairs are on Layer 1 and 3 and Layer 2 is GND, then there is no change in GND reference plane for the Layer 1 ­ 3 transitions. If the layer changes result in a change in GND reference planes, then there need to be GND stitching vias close to the trace vias. The stitching vias tie the GND planes together in the vicinity of the signal pair layer transition. 7 It is critically important that the + and ­ signal lines in a differential pair are closely length matched. The matching is on the order of a few mils for the faster interfaces. This is sometimes called intra-pair length matching. In this document, this is referred to as differential pair + and ­ length matching. The different pairs in a group (e.g. the four TX+ and ­ pairs in x4 PCIe link) do not need to be matched very closely at all for many modern interfaces. This is sometimes called inter-pair length matching. In this document, it is referred to as pair to pair length matching (or similar). For some interfaces, this mismatch can be on the order of inches. 8 Coupling capacitors should be discrete 0402 or 0201 package size parts. Do not use capacitor arrays as these can have internal cross coupling that can severely attenuate the differential signal. 9 The plane under the coupling capacitors for the higher speed interfaces should be voided (meaning that rectangular holes about the same size as the capacitor lands, or slightly larger, should be created in the plane) ­ whether it is a GND or PWR plane. See the Intel Document 627205 referenced in Table 22 above for details. 10 Plane layers that do NOT connect to a particular via should be voided with a circular void around the via barrel. This is done anyway so that the plated via hole does not connect to the plane, but the void should be expanded somewhat to avoid signal coupling to the plane. See the Intel Document 627205 referenced in Table 22 above for details.

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PCB Design Rule Summaries
Ref Rule / Recommendation 11 High speed traces should not be run close to the board edges, especially for long runs parallel to the edge. If
they are run this way, they may be creating an EMI hazard. 12 Sometimes the differential pairs are serpentined to adjust the pair length to match another pair. There is usually
a "minimum distance to self", listed in some of the Tables below. 13 The fastest interfaces need to account for the "Fiberweave Effect". This effect is due to the periodic variations in
the PCB material dielectric constant caused by the fiberglass weave pattern within a PCB layer. The mitigation strategies are to either arrange that the PCB routes are not parallel (in x or y) to the glass fibers in the weave, or to use a PCB material that does not show this effect. Some of the references in Table 22 have details and illustrations on this effect.

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PCB Design Rule Summaries

4.3.

PCB Design Rule Summaries - High Speed Differential Pair Serial Interfaces

The COM-HPC high speed serial interfaces and two of the fastest single ended interfaces were extensively simulated by a Signal Integrity subgroup during the development of the COM-HPC specification. These efforts resulted in a set of loss budgets, maximum trace length values and other related recommendations. This is documented in Section 6 of the COM-HPC Base Specification. The loss-budget approach allows the findings to be adapted to various different PCB materials (e.g. Standard Loss, Mid Loss, Low Loss and Very Low Loss).
The Base Specification recommendations as they apply to COM-HPC Carrier designs are summarized in the Sections below . Some recommendations such as trace length matching requirements are not found in the Base Specification document; rather they are compiled from industry sources.

4.3.1.

NBASE-T Design Rule Summary

Table 24: NBASE-T Design Rule Summary
Ref Parameter Description 1 Signaling Rate / Nyquist Frequency

2 Preferred PCB Routing Environment

3 Differential Trace Impedance 4 Single Ended Trace Impedance 5 Max Module Trace Length
6 Max Carrier Trace Length
7 Differential Pair +/- Length Matching (Carrier / Module) 8 TX Pair to TX Pair Length Matching (Carrier / Module) 9 RX Pair to RX Pair Length Matching (Carrier / Module) 10 TX Pair to RX Pair Length Matching (Carrier / Module) 11 TX Pair to RX Pair Spacing (Carrier / Module) 12 TX or RX pair Spacing to Other Signals 13 Max Via Stub Length

Parameter Value 1000BASE-T: 250 Mbps / ~80 MHz 10GBASE-T: 2.5 Gbps / ~450 MHz Asymmetric Stripline Unbroken GND plane primary reference
Microstrip routing may be used Microstrip is necessary near connectors
Quiet unbroken well bypassed power plane may be used as a reference plane. 100 ohm +/- 10%
55 ohm +/- 15% 1GBASE-T STD Loss PCB Material:  3000 mils 10GBASE-T STD Loss PCB Material:  1500 mils 10GBASE-T MID Loss PCB Material:  1500 mils 1GBASE-T STD Loss PCB Material:  5000 mils 10GBASE-T STD Loss PCB Material:  2500 mils 10GBASE-T MID Loss PCB Material:  4500 mils 5 mil / 5 mil 500 mil / 500 mil 500 mil / 500 mil 500 mil / 500 mil D  5*H (Asymmetric Stripline) DX  8*H (Asymmetric Stripline) 80 mil

See Figure 61 above for definitions of D, DX and H.

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PCB Design Rule Summaries

4.3.2.

Ethernet KR Design Rule Summary

Table 25: Ethernet KR Design Rule Summary

Ref Parameter Description

Parameter Value

1 Signaling Rate / Nyquist Frequency

10G KR: 10.3125 Gtps / ~5.1 GHz 25G KR: 25.78125 Gtps / ~12.9 GHz 40G KR4: 10.3125 Gtps / ~5.1 GHz 100G KR4: 25.78125 Gtps / ~12.9 GHz

2 Preferred PCB Routing Environment

Asymmetric Stripline Unbroken GND plane primary reference

3 Differential Trace Impedance

93 ohm +/- 10%

4 Single Ended Trace Impedance

50 ohm +/- 15%

5 Maximum Trace Lengths on Carrier (adapted from COM-HPC Base Specification V1.0 Tables 79, 81, 83)

PHY Down on Carrier
Carrier Trace Lengths 10GBASE-KR 25GBASE-KR RS-FEC 25GBASE-KR BASE-R FEC 25GBASE-KR No FEC

Budget (dB)
16.0 20.0 16.0
12.0

Standard Loss (SL) PCB Material (inches) 13.2 7.9 6.3

Mid Loss (ML) PCB Material (inches) 21.0 12.9 10.3

Low Loss (LL) PCB Material (inches) 27.4 16.5 13.2

Very Low Loss (VLL) PCB Material (inches) 37.3 23.1 18.5

4.7

7.8

9.9

13.8

Module1 MAC to Module2 MAC Carrier Trace Lengths 10GBASE-KR 25GBASE-KR RS-FEC 25GBASE-KR BASE-R FEC 25GBASE-KR No FEC

Budget (dB)
12.0 12.0 8.0
3.0

Standard Loss (SL) PCB Material (inches) 9.9 4.7 3.2

Mid Loss (ML) PCB Material (inches) 15.7 7.8 5.2

Low Loss (LL) PCB Material (inches) 20.5 9.9 6.6

Very Low Loss (VLL) PCB Material (inches) 28.0 13.8 9.2

1.2

1.9

2.5

3.5

SFP Connector on Car- Budget

rier

(dB)

Carrier Trace Lengths

SFP+ Max Carrier Trace 1.50

SFP28 Max Carrier Trace 2.00

Standard Loss (SL) PCB Material (inches) 1.24 0.79

Mid Loss (ML) PCB Material (inches) 1.97 1.29

Low Loss (LL) PCB Material (inches) 2.56 1.65

Very Low Loss (VLL) PCB Material (inches) 3.50 2.31

6 Differential Pair +/- Length Matching (Carrier / Module) Note the very tight matching for 25GBASE-KR This is actually relaxed from some Intel recommendations, per PICMG consultation with Intel
7 TX Pair to Pair Length Matching (Carrier / Module) 8 RX Pair to Pair Length Matching (Carrier / Module) 9 TX Pair to RX Pair Length Matching (Carrier / Module) 10 TX Pair to RX Pair Spacing (Carrier / Module) 11 TX or RX pair Spacing to Other Signals 12 Max Via Stub Length

2.5 mil / 2.5 mil for 10GBASE-KR 1.5 mil / 1.5 mil for 25G BASE-KR
500 mil / 500 mil (KR4 only; N/A for KR) 500 mil / 500 mil (KR4 only; N/A for KR) 500 mil / 500 mil D  5*H (Asymmetric Stripline) DX  8*H (Asymmetric Stripline) 10 mil (KR and KR4)

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PCB Design Rule Summaries

4.3.3.

SATA Design Rule Summary

Table 26: SATA Design Rule Summary

Ref Parameter Description

Parameter Value

1 Signaling Rate / Nyquist Frequency

Gen 1: 1.5 Gtps / 0.75 GHz Gen 2: 3 Gtps / 1.5 GHz Gen 3: 6 Gtps / 3 GHz

2 Preferred PCB Routing Environment

Asymmetric Stripline Unbroken GND plane primary reference

3 Differential Trace Impedance

85 ohm +/- 10%

4 Single Ended Trace Impedance

45 ohm +/- 15%

5 Maximum Trace Lengths (from COM-HPC Base Specification V1.0 Tables 58 and 60 )

Device Up on M.2 or mSATA Card
SATA Gen1 Carrier Trace SATA Gen2 Carrier Trace SATA Gen3 Carrier Trace

Budget
dB 1.1 1.8 2.9

Standard Loss (SL) Mid Loss (ML)

PCB Material

PCB Material

Inches

Inches

4.07

6.88

3.91

6.55

3.74

6.03

Low Loss (LL) PCB Material Inches 8.46 8.14 7.80

Very Low Loss (VLL) PCB Material Inches 9.17 10.11 10.21

Cabled Interface
SATA Gen1 Carrier Trace SATA Gen2 Carrier Trace SATA Gen3 Carrier Trace

Budget
dB 0.7 1.1 1.8

Standard Loss (SL) Mid Loss (ML)

PCB Material

PCB Material

Inches

Inches

2.59

4.38

2.39

4.00

2.32

3.74

Low Loss (LL) PCB Material Inches 5.38 4.98 4.84

Very Low Loss (VLL) PCB Material Inches 5.83 6.18 6.34

6 Differential Pair +/- Length Matching (Carrier / Module) 7 TX Pair to RX Pair Length Matching (Carrier / Module) 8 TX Pair to RX Pair Spacing (Carrier / Module) 9 TX or RX pair Spacing to Other Signals 10 Max Via Stub Length

2.5 mil / 2.5 mil to support SATA Gen 3 No requirement D  5*H (Asymmetric Stripline) DX  8*H (Asymmetric Stripline) 80 mil

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4.3.4.

PCIe Design Rule Summary

Table 27: PCIe Design Rule Summary

Ref Parameter Description

Parameter Value

1 Signaling Rate / Nyquist Frequency

Gen 3: 8 Gtps / 4 GHz Gen 4: 16 Gtps / 8 GHz Gen 5: 32 Gtps / 16 GHz

2 Preferred PCB Routing Environment

Asymmetric Stripline Unbroken GND plane primary reference

3 Differential Trace Impedance (PCIe data and Ref CLK pairs) 85 ohm +/- 10%

4 Single Ended Trace Impedance

45 ohm +/- 15%

5 Maximum Trace Lengths (from COM-HPC Base Specification V1.0 Tables 52 and 54)

Device Down

Budget (dB)

Gen 3 Max Carrier Trace Gen 4 Max Carrier Trace Gen 5 Max Carrier Trace

11.00 12.50 13.00

Standard Loss (SL) PCB Material (inches) 10.37 7.11 4.23

Mid Loss (ML) PCB Material (inches) 15.65 10.77 6.86

Low Loss (LL) PCB Material (inches) 20.16 13.44 8.97

Very Low Loss (VLL) PCB Material (inches) 26.68 17.64 12.65

Device Up

Budget (dB)

Gen 3 Max Carrier Trace 6.50 Gen 4 Max Carrier Trace 7.50 Gen 5 Max Carrier Trace 8.00

Standard Loss (SL) PCB Material (inches) 6.13 4.26 2.60

Mid Loss (ML) PCB Material (inches) 9.25 6.46 4.22

Low Loss (LL) PCB Material (inches) 11.91 8.06 5.52

Very Low Loss (VLL) PCB Material (inches) 15.77 10.58 7.78

6 Differential Pair +/- Length Matching (Carrier / Module) 7 TX Pair to TX Pair Length Matching (Carrier / Module)
RX Pair to RX Pair Length Matching (Carrier / Module) 8 TX Pair to RX Pair Length Matching (Carrier / Module) 9 TX Pair to RX Pair Spacing 10 TX or RX pair Spacing to Other Signals 11 PCIe Data Pair Distance to Self 12 PCIe RX or TX Data Pair Length relative to PCIe Reference
Clock Pair Length 13 Maximum Via Stub Lengths:
14 Land Pattern and Via Voiding Recommendations:
15 Fiberweave Effect Mitigation

Gen 3, 4, 5:  2.5 mil / 2.5 mil Gen 3, 4, 5:  500 mil / 500 mil
No TX to RX matching required Gen 3, 4, 5: D  5H Gen 3, 4, 5: DX  8H Gen 3, 4, 5: D  3W No matching required. The Reference Clock Pairs should be routed as directly as possible. Gen 3:  80 mil Gen 4:  30 mil Gen 5:  10 mil Gen 3, 4, 5: planes adjacent to component lands should be voided. All layers that a PCIe coupling via passes through should be voided, unless the via connects on that layer. See the Intel Document 627205 referenced in Table 22 above for illustrations on voiding and length matching. See Fiberweave Effect references in Table 22 above. Alternatively, use a PCB material that does not exhibit this effect.

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4.3.5.

USB 2.0 Design Rule Summary

Table 28: USB 2.0 Design Rule Summary
Ref Parameter Description 1 Signaling Rate / Nyquist Frequency 2 PCB Routing Environment

3 Differential Trace Impedance (USB 2.0 data pair) 4 Single Ended Trace Impedance 5 Max Carrier Trace Length
6 Differential Pair +/- Length Matching (Carrier / Module) 7 Pair Spacing to other USB 2.0 Pairs (Carrier / Module) 8 TX or RX pair Spacing to Other Signals 9 Max Via Stub Length

PCB Design Rule Summaries

Parameter Value 480 Mbps / 240 MHz (USB 2.0 High Speed) Asymmetric Stripline is best Microstrip may be used

Unbroken GND plane primary reference is best Quiet PWR plane may be used as a reference

Plane splits should be avoided If plane splits are unavoidable, stitching capacitors should be used to tie the plane regions together, for AC signals

90 ohm +/- 10%

Circa 45 to 50 ohm

Cabled Interface:

14 inches

Device Down on Carrier: 28 inches

20 mil / 20 mil

D  5*H (Asymmetric Stripline)

DX  8*H (Asymmetric Stripline)

80 mil

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4.3.6.

USB 3.2 and USB4 Design Rule Summaries

Table 29: USB 3.2 and USB4 Design Rule Summaries

Ref Parameter Description

Parameter Value

1 Signaling Rate / Nyquist Frequency

USB 3.2 Gen 1: USB 3.2 Gen 2: USB4 Gen 2: USB4 Gen 3:

5 Gtps / 2.5 GHz 10 Gtps / 5 GHz 10 Gtps / 5 GHz 20 Gtps / 10 GHz

2 Preferred PCB Routing Environment

Asymmetric Stripline Unbroken GND plane primary reference

3 Differential Trace Impedance (USB SuperSpeed Pairs)

USB 3.2 Gen 1: Historically was 90 ohm Going forward, 85 ohm is OK
USB 3.2 Gen 2: 85 ohm +/- 10% USB4 Gen 2: 85 ohm +/- 10% USB4 Gen 3: 85 ohm +/- 10%

4 Single Ended Trace Impedance

45 ohm +/- 15%

5 Maximum Carrier Trace Lengths (from COM-HPC Base Specification V1.0 Tables 67 and 69 )

USB SuperSpeed Device Down
USB 3.2 Gen 1 USB 3.2 Gen2 USB4 Gen 2 USB4 Gen 3

Budget (dB)
3.2 5.5 5.5 10.5

Standard Loss (SL) PCB Material (Inches) 4.7 4.7 4.7 5.2

Mid Loss (ML) PCB Material (Inches) 7.6 7.6 7.6 7.6

Low Loss (LL) PCB Material (Inches) 10 9.8 9.8 10.7

Very Low Loss (VLL) PCB Material (Inches)
12.8 13.4 13.4 15

USB SuperSpeed Cabled Interface
USB 3.2 Gen 1 USB 3.2 Gen 2 USB4 Gen 2 USB4 Gen 3

Budget (dB)
3.2 5.5 5.5 10.5

Standard Loss (SL) PCB Material (Inches) 4.7 4.7 4.7 NA

Mid Loss (ML) PCB Material (Inches) 7.6 7.5 7.5 NA

Low Loss (LL) PCB Material (Inches) 10 9.8 9.8 NA

Very Low Loss (VLL) PCB Material (Inches)
12.8 13.4 13.4 NA

The values marked in red in the Table just above indicate that there is insufficient overall margin for a direct cabled interface with USB 3.2 Gen 2 or USB4 Gen 2 or USB4 Gen 3. Redrivers or retimers placed close to the cable connectors are advised. The Carrier maximum trace lengths in the Device Down Table above may be used for the run between the COM-HPC Module and the redrivers or retimers.

6 Differential Pair +/- Length Matching (Carrier / Module)

 2.5 mil / 2.5 mil

7 TX Pair to TX Pair Length Matching (Carrier / Module) RX Pair to RX Pair Length Matching (Carrier / Module)

 100 mil / 100 mil Applies only to x2 configurations (2 TX pairs and 2 RX pairs)

8 TX Pair to RX Pair Length Matching (Carrier / Module)

 100 mil / 100 mil

9 TX Pair to RX Pair Spacing

D  5H

10 TX or RX pair Spacing to Other Signals

DX  8H

11 TX or RX Data Pair Distance to Self

13 Maximum Via Stub Lengths:

USB 3.2 Gen 1  80 mil USB 3.2 Gen 2  30 mil USB4 Gen 2  30 mil USB4 Gen 3  10 mil

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Ref Parameter Description 14 Land Pattern and Via Voiding Recommendations:
15 Fiberweave Effect Mitigation

Parameter Value

PCB Design Rule Summaries

Gen 3, 4, 5: planes adjacent to component lands should be voided. All layers that a coupling via passes through should be voided, unless the via connects on that layer. See the Intel Document 627205 referenced in Table 22 above for illustrations on voiding and length matching. See Fiberweave Effect references in Table 22 above. Alternatively, use a PCB material that does not exhibit this effect.

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4.3.7.

DisplayPort Design Rule Summary

Table 30: DisplayPort Design Rule Summary
Ref Parameter Description 1 Preferred PCB Routing Environment

Parameter Value Asymmetric Stripline Unbroken GND plane primary reference

Microstrip is necessary in region near DP connector

2 Differential Trace Impedance

85 ohm +/- 10%

3 Single Ended Trace Impedance

45 ohm +/- 15%

4 Maximum Carrier Trace Lengths (adapted from COM-HPC Base Specification V1.0 Tables 86 and 87 )

DisplayPort Cabled Interfaces No Carrier Redriver DP HBR DP HBR2 DP HBR3 DP UHBR10 DP UHBR13.5 DP UHBR20

Bit Rate / Nyquist (per Lane) Gbps / GHz
2.7 / 1.3 5.4 / 2.7 8.1 / 4.0 10 / 5.0 13.5 / 6.7 20 / 10

Standard Loss PCB Material inches
3.2 2.9 2.3 1.65 1.8 1.3

Mid Loss PCB Material inches
5.4 4.6 3.6 2.6 3.0 2.2

Low Loss PCB Material inches
6.7 6.0 4.7 3.4 3.8 2.8

Very Low Loss PCB Material inches
8.3 7.8 6.3 4.6 5.3 3.8

DisplayPort With Carrier Retimer/Redriver DP2.0 UHBR13.5 DP2.0 UHBR20

Bit Rate / Nyquist (per Lane) Gbps / GHz
13.5 / 6.7 20 / 10

Standard Loss PCB Material inches
5 3.7

Mid Loss PCB Material inches
8 6

Low Loss PCB Material inches
10.4 7.6

Very Low Loss PCB Material inches
14.4 10.7

Red text in upper table above indicates that there is insufficient margin in the overall channel and that that particular configuration should not be used.

5 Differential Pair +/- Length Matching (Carrier / Module)

 2.5 mil / 2.5 mil

6 Data Pair to Pair Length Matching (Carrier / Module)

 100 mil / 100 mil

7 Pair to Pair Spacing

D  5H

8 TX or RX pair Spacing to Other Signals

DX  8H

9 TX or RX Data Pair Distance to Self

10 Maximum Via Stub Lengths:

80 mil (per lane bit rate  5.4 Gtps) 30 mil (per lane bit rate  13.5 Gtps) 10 mil (per lane bit rate 20 Gtps)

11 Land Pattern and Via Voiding Recommendations:

For DP modes with bit-rate at or above 8 Gtps per lane:

Planes adjacent to component lands should be voided. All layers that a coupling via passes through should be voided, unless the via connects on that layer. See the Intel Document 627205 referenced in Table 22 above for illustrations on voiding and length matching.

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4.3.8.

eDP Design Rule Summary

PCB Design Rule Summaries

Embedded DisplayPort signal integrity considerations were not explicitly addressed by the COM-HPC Signal Integrity subgroup. As such, it would be reasonable for COM-HPC Carrier designers to use the COM-HPC DisplayPort Design Rule Summary outlined in Section 4.3.7. for eDP layouts. For eDP panels, only the lower bit rate formats (HBR, HBR2, HBR3) are likely to come into play.
Alternatively, Carrier Designers can consult some of the Intel and AMD Design Guides listed in Table 22 above for eDP guidance. The Intel Document 627205 in particular has lots of eDP advice. However, these Design Guides are targeting laptop and motherboard designs and it can be tricky to map these recommendations to the COM-HPC system case. The general rule of thumb is that about half of the motherboard or laptop board budget goes to the COM-HPC Module and half to the COM-HPC Carrier.

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4.3.9.

HDMI Design Rule Summary

PCB Design Rule Summaries

Table 31: HDMI Design Rule Summary
Ref Parameter Description 1 Preferred PCB Routing Environment

Parameter Value Asymmetric Stripline Unbroken GND plane primary reference

Microstrip may necessary in the region near the HDMI connector

2 Differential Trace Impedance

85 ohm +/- 10% (on Carrier before HDMI buffer) 100 ohm +/- 10% (after buffer)

3 Single Ended Trace Impedance

45 ohm +/- 15% (before buffer) 55 ohm +/- 15% (after buffer)

4 Maximum Carrier Trace Lengths (adapted from COM-HPC Base Specification V1.0 Table 88) )

HDMI Buffer / Driver Bit Rate / Nyquist

on Carrier near

(per Lane)

HDMI Connector

Gbps / GHz

HDMI 1.4

3 / 1.5

HDMI 2.1

6 / 3

HDMI 2.1

12 / 6

Standard Loss PCB Material inches
4

Mid Loss PCB Material inches

Low Loss PCB Material inches

Very Low Loss PCB Material inches

5.75

6.75

10

5 Differential Pair +/- Length Matching (Carrier / Module) 6 Data Pair to Pair Length Matching (Carrier / Module) 7 Pair to Pair Spacing 8 TX or RX pair Spacing to Other Signals 9 TX or RX Data Pair Distance to Self 10 Maximum Via Stub Lengths:
11 Land Pattern and Via Voiding Recommendations:

 2.5 mil / 2.5 mil  100 mil / 100 mil D  5H DX  8H
80 mil (per lane bit rate  6 Gtps) 30 mil (per lane bit rate = 12 Gtps) For HDMI modes with bit-rate at 12 Gtps per lane: Planes adjacent to component lands should be voided. All layers that a coupling via passes through should be voided, unless the via connects on that layer. See the Intel Document 627205 referenced in Table 22 above for illustrations on voiding and length matching.

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4.4.

PCB Design Rules for Single Ended (SE) Interfaces

PCB Design Rule Summaries

Table 32: Design Rules for Single Ended Interfaces

Ref Rule / Recommendation

1 Most COM-HPC SE traces may be routed using a 55 ohm +/- 15 %. trace impedance. The BOOT_SPI_xxx , eSPI_xxx and GP_SPI_xxx nets are the exceptions and should be routed as 50 ohm +/- 15%

2 SE nets may be routed as Stripline or Microstrip traces, referenced to a GND plane or to a quiet PWR plane.

3 Crossing plane splits should be avoided for the faster SE interfaces (BOOT_SPI_xxx, eSPI_xxx and GP_SPI_xxx). If these nets do cross a split in the reference plane, then the split should be "stitched" with a small capacitor that bridges the split for AC signals.

4 SE signals with higher bit rates and faster edge rates need more routing care than slower signals. The higher bit

rate SE signals include:

· BOOT_SPI_xxx

Up to circa 100 Mhz in some cases; up to circa 50 MHz is more typical

· eSPI_xxx

Up to circa 50 MHz

· GP_SPI_xxx

Up to circa 50 MHz

· I3C

Up to circa 33 MHz

· Soundwire

Up to circa 12 MHz

· Various I2C signals

Up to circa 1 MHz or 400 kHz in some cases but more typically are 100 kHz max

· UART_xxx

Up to circa 1 MHz in some cases ­ usually less ­ 115 kHz max is more common

COM-HPC SE signals not listed just above are likely to be very slow, almost static in many cases.

"More routing care" can mean:

· Signal should be GND referenced

· No plane split crossings

· Stripline routing preferred, with primary reference to GND

· Series damping resistors for the signals listed as 50 MHz or more

· BOOT_SPI_xxx, eSPI_xxx and GP_SPI_xxx have specific routing rules (see below)

5 The COM-HPC BOOT_SPI_xxx signals are arranged in a "balanced tree" topology. Full details can be found in the COM-HPC Base Specification Version 1.0 Section 6.11.1. Up to 4 BOOT_SPI_xxx devices are allowed, but 3 are on the Module and only 1 (or 0) are allowed on the Carrier. The trace lengths for the BOOT_SPI Data and Clock between the COM-HPC connector balls and the Carrier device must be at least 2000 mils long and no more than 3000 mils long. This is to "balance" the on-Module and off-Module branches of the tree. The Data and Clock lines for this branch of the tree should be length matched to within 250 mil. A series damping resistor is recommended. Refer to the COM-HPC Base specification for more details and a diagram. The Chip Select line associated with the Carrier BOOT_SPI_xxx signals does not need length matching and should be routed as directly as possible.

6 The COM-HPC eSPI_xxx signals are arranged in a "balanced tree" topology. Full details can be found in the COMHPC Base Specification Version 1.0 Section 6.11.2. Up to 4 eSPI_xxx devices are allowed: up to 2 on the Module and up to 2 on the Carrier. The trace lengths for the eSPI Data and Clock lines between the COM-HPC connector balls and the Carrier device(s) must be at least 2000 mils long and no more than 3000 mils long. This is to "balance" the on-Module and off-Module branches of the tree. A series damping resistor is recommended. There should be separate branches in the tree if there are 2 Carrier devices. Refer to the COM-HPC Base specification for more details and a diagram. The Chip Select line associated with the Carrier eSPI_SPI_xxx signals does not need length matching and should be routed as directly as possible.

7 GP_SPI_xxx net routing should follow the same rules as the eSPI_xxx nets. If there are 2 GP_SPI devices, there should be 2 separate tree branches.

8 If any SE signals leave the Carrier and are exposed to the outside world and to potential contact with users, there should be both EMI and ESD mitigation measures implemented close to the connectors that face outside.

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5.

Mechanical Considerations

Mechanical Considerations

5.1.

Heat Spreader / Module / Carrier Attachment Details

5.1.1.

Heat Spreader to Module Attachment Notes

The COM-HPC Base Specification calls out Module PCB mounting holes that are are to align with corresponding Heat Spreader Plate, Carrier board and possibly system chassis mounting holes or features to hold the entire assembly together.
However, the COM-HPC Base Specification also recommends that there be a separate set of vendor-specific holes to secure the Heat Spreader Plate (HSP), the Thermal Interface Materials (TIM) and the COM-HPC Module board together as a subsystem that can be shipped as a unit, independent of the larger system that includes the Carrier and other components (chassis, heat sinks, etc.). This is desirable as the TIM stack can be a sensitive, precision assembly that is best handled once and only once by the Module vendor.
The reference to separate, design specific holes in the Module and HSP for this purpose are in the COM-HPC Base Specification V1.0 in Section 7.5.4 Table 93 Ref 5, reproduced here:
The implementation specific holes / spacers / standoffs used to secure the HSP to the Module should be different from those used at the COM-HPC defined mounting hole sites.
The x-y positions, the number of the vendor-specific HSP / TIM / Module attachment points and other implementation details are not defined by the COM-HPC specification document. However, a typical vertical cross section diagram of how this can be implemented is shown in Figure 62 below.
Figure 62: Vendor Specific Heat Spreader to Module Attachment ­ Bottom Side Module PCB Access

Legend:

Heat Spreader Plate ­ Vendor Specific Implementation Details HSP to Module Spacers or Standoffs ­ Vendor Specific Locations and Implementation Details TIM ­ Vendor Specific Implementation Details ­ Typically, Compliant Foam or Phase Change Material CPU / SOC Die or Lid Module PCB Spacers / Standoffs at COM-HPC Defined X-Y Positions, For Module Mounting ­ Vendor Specific Implementation Details Module to Carrier Connectors

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Mechanical Considerations

5.1.2.

Heat Spreader / Module Assembly Attachment to Carrier and Chassis

Figures 63 through 66 illustrate a variety of hardware mechanical component and assembly options to secure the COM-HPC HSP, Module, Carrier and system chassis together,

Figure 63: Heat Spreader Assembly Mounting to Carrier ­ Bottom Side Screw Access

Detail B

Cross section view of Detail B
HSP Stand-Off (M2.5 thread) Carrier Board Stand-Off (Ø 2.7 clearance hole)
M2.5 Screw and Washer

Heatspreader (HSP)
CPU Module Carrier Board

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Mechanical Considerations Figure 64: Heat Spreader Assembly Mounting to Carrier ­ Top Side Screw Access
Detail A

Cross section view of Detail A
M2.5 Screw (flat head)
HSP Stand-Off (Ø 2.7 clearance hole)
Baseboard Stand-Off (M2.5 thread)

Heatspreader (HSP)
CPU Module Carrier Board

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Mechanical Considerations Figure 65: Heat Spreader Assembly Mounting to Carrier With Broaching Nut ­ Top Side Screw Access
Detail A

Cross section view of Detail A
M2.5 Screw (flat head)
Heatspreader Stand-Off (Ø 2.7 clearance hole)
Broaching Stand-Off (M2.5 thread)

Heatspreader CPU Module Carrier Board

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Mechanical Considerations Figure 66: Heat Spreader Assembly Mounting to Carrier and Chassis ­ Top Side Screw Access
Detail A

Cross section view of Detail A
M2.5 Screw (flat head)
Heatspreader Stand-Off (Ø 2.7 clearance hole) Carrier Board Stand-Off (Ø 2.7 clearance hole) Broaching Stand-Off (M2.5 thread)

Heatspreader CPU Module Carrier Board Chassis

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Mechanical Considerations
Some useful vendors and vendor part numbers for mechanical parts that may be used in Figures 63 through 66 above are listed here:
 PEM TSOS-M25-1500  M2.5 threaded blind standoff for sheet metal / plate use - 15 mm overall length (for Client)
 PEM TSOS-M25-1800 (18 mm for Server)  M2.5 threaded blind standoff for sheet metal / plate use - 18 mm overall length (for Server)
 www.pemnet.com
 Wurth 9774050951 5 mm Length x 5.1 mm OD x 2.7 mm ID SS SMT Clearance Hole Spacer  Wurth 9774100951 10 mm Length x 5.1 mm OD x 2.7 mm ID SS SMT Clearance Hole Spacer
 May be SMT soldered to Carrier Top side as shown in the Figures 63 and 66 above  www.wuerth.com
 EFCO (Taiwan) has numerous mechanical parts for COM-HPC and other Module standards  www.efcotec.com  Or use a search engine, look for " efcotec com accessories "

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Mechanical Considerations

5.2.

Alternative COM-HPC Board Stack Assembly Suggestion

An alternative COM-HPC board stack assembly method and set of mechanical hardware is presented just below. This material has been submitted by Samtec. These assembly mechanics make use of Samtec defined connector hardware components, known as JSOM, for "Jack Screw Stand-off ­ Micro". These mechanical hardware parts are used in PC-104 and in some VITA assemblies. Samtec JSOM data sheets and drawings are readily available online.
This approach defines an assembly stack allowing a COM-HPC Module and Carrier to be mounted to a metal chassis which is below the Carrier. This assembly method does not include considerations for a Heat Spreader Plate. Thermal management components such as heat sinks or HSP / heat sink combinations would be handled on separate holes.
The `ASP' references in some of the Figures below are Samtec designations for "Application Specific Parts". There is an ASP summary in Figure 73 several pages below.

5.2.1.

Precision Jack Screw Standoffs

Precision jack screw standoff hardware (referred to as JSOM by Samtec) can be used to help mating and unmating procedures in high-normal-force, multi-connector applications. They work like traditional stand-offs but contain an internal machined hex screw that can be turned in a counterclockwise direction to lift the Module Card from the Carrier Board. JSOM based assemblies can mitigate damage to the connector pins, components, boards, and solder joints.
Assembly / Dis-assembly Procedure Overview
Before mating the Module Card to the Carrier Board, use a 1.5mm hex driver to turn the JSOM screw clockwise until the screw is fully seated in the JSOM standoff.
Figure 67: JSOM (Jack Screw Standoff ­ Micro) Diagram and Application Cutaway

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Mechanical Considerations
Once all four JSOM screws are fully seated, apply even downward pressure over the J1 and J2 connector regions to mate the Module Card to the Carrier Board. Once the Module Card is fully mated secure the Module Card to the Carrier Board with four hex nuts and lock washers as shown in Figure 68 (a). Use a torque wrench to tighten the hex nuts to 3.0 (+/- 0.5) in-lbs. Tighten the nuts in an alternating diagonal pattern shown in Figure 68 (b). For detailed mating recommendations, refer to section 7.5.5 of the COMHPC® Module Base Specification, Revision 1.0. Figure 68: (a) Hex Nuts to Torque (b) Diagonal Torque Application / De-application (c) Hex Screw Turns
Figure 3. (a) Hex nut torque, (b) diagonal unmate pattern, (c) hex screw turning ratio
Unmating the Module Card from the Carrier Board To unmate the boards remove the locking nuts and washers. Using the diagonal pattern shown in Figure 68 (b) insert the 1.5mm hex key shown in Figure 68 (c) into the JSOM screw labeled 1 and turn counterclockwise a ¼ turn. Repeat this procedure for all JSOM screws labeled 2, 3, and 4 until the connectors unmate. The Module Card can then be removed from the Carrier Board. Figure 69: COM-HPC Stack Dis-assembly Procedure Using JSOM Hardware

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Mechanical Considerations

5.3.

Carrier Board Stiffener

FEM (Finite Element Method) mechanical simulations were conducted to understand the amount of deflection and temporary stress that can occur in the Carrier Board as it is being mated with a Module Card. The simulations assumed that the Carrier Board was fabricated using standard 0.0625" thick FR4 material and fixed to a stiff chassis using metal stand-offs attached to the mounting holes adjacent to both the Carrier P1 and P2 connectors. As shown in Figure 70, a downward force was applied evenly over the length of the connector, and the amount of deflection was measured. The results confirmed that 0.0625" Carrier Boards should be supported using some type of stiffening mechanism.

Figure 70: FEM Simulation Results ­ 0.0625" FR4 Carrier ­ No Stiffener

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Mechanical Considerations
Note however that the stiffness of a piece of sheet material such as a PCB is proportional to the cube of the sheet thickness. Hence using a thicker PCB may relax or obviate the need for a Carrier stiffener. PCB thickness of 0.079" (2mm), 0.092" and even 0.125" are common. However, be aware that if the Carrier uses through hole parts (typically for I/O connectors) then increasing the PCB thickness too much will result in a soldering problem as the through hole part leads need protrude beyond the PCB a bit for wave soldering.
A metal simple stiffener design is shown in Figure 71 below with the corresponding keep-out regions shown in Figure 72. This Figure shows the Carrier PCB Top side. The Carrier stiffener keep-out regions are on the Bottom side of the Carrier board, as indicated by the dashed lines.
When designing a Carrier Board stiffener there are some points to consider.
 The stiffener should provide uniform support directly underneath the Carrier Board connector and span the entire length of the connector region. This should be done for both the P1 and P2 Carrier connectors.
 The stiffener should be securely anchored to the chassis through mechanical mounting hardware or attached to the bottom side of the Carrier Board using an adhesive.
 The stiffener thickness should be as thick as the application allows.  Care must be taken when using conductive materials such as steel or alloys.  This stiffener concept will require a keep-out region where peripheral components cannot be placed.  It may be necessary to exclude via pads from the PCB Bottom side in the in the keep-out region, or
to insulate vias from a metallic stiffener. Kapton tape is the usual remedy for this situation. But such a solution may not be appropriate for high ­ vibration situations. A thicker, compliant foam material may also be considered.
Figure 71: Mechanical Carrier Stiffener Possibility

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Figure 72: Carrier Board Stiffener Keep-Out Region (Seen Through Carrier)

Mechanical Considerations

Dimensions in the two Figures above are in mm.

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Figure 73: Application Specific Part Number (ASP) Reference Guide

Mechanical Considerations

Non-Metallic Stiffener Possibilities
A simple but effective Carrier board stiffener option is to fabricate a simple non-metallic rectangular bar that is positioned between the Carrier PCB Bottom side and the system chassis. The stiffener bar extent shadows the Carrier connector and the adjacent mounting holes as shown by the dashed lines in Figure 72 above. Nylon is a suitable material. Metal press fit inserts at the mounting hole positions may be beneficial.

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6.

Appendices

Appendices

6.1.

Appendix A: Synchronous Ethernet

Synchronous Ethernet, or SyncE, is an ITU-T standard that allows precision timing information to be embedded into Ethernet physical layer. This signal can be correlated to an external high precision master clock. It is important to telecom providers as the telecom infrastructure moves away from TDM based standards such as SONET and to packet based Ethernet implementations.

Introduction to SyncE
· Synchronous Ethernet (SyncE) distributes a frequency signal through Ethernet - Defined in ITU-T G.8261, G.8262, G.8262.1, G.8264
· GbE and above always sends symbols (data or idle) · SyncE recovers received data rate
- Ethernet requires ±100 ppm clocking - Receivers must handle up to 200 ppm clock delta - SyncE saves off a fractional rate to drive DPLL
External DPLLs
· External DPLLs can take in multiple clock sources - 1PPS and 10 MHz inputs­GPS/GNSS input(s) - often 1PPS as well - SyncE recovered clocks - IEEE 1588/PTP-driven clocks (also often 1PPS) - Local oscillator - Long-term oscillator (TCXO or OCXO)
· DPLL sets a priority of inputs · All outputs driven synchronously off selected input(s)
-TX side of all PHYs and/or SoCs driven from PLL clock
SyncE on PHYs
· Some SoCs support SyncE on internal PHYs · Some external PHYs support SyncE clock recovery · Each RX port adapts to meet incoming data rate
- Each RX port may be different - Fractional clock rate from selected port(s) sent to DPLL · Tx side driven from DPLL - All TX ports driven at same rate · Driver support for SyncE with external DPLLs may vary
Implications for Modules / Pin-outs
· If Module SoC and Carrier Board PHY both need SyncE, need SyncE info across connectors · Carrier sends recovered clock(s), 1PPS input(s) · Module sends TX clock(s), 1PPS output(s)

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Figure 74: Synchronous Ethernet Overview

Appendices

SDA SCL

OUT0p

PPS Output

OUT1p

10M Sync Clock Output

SMA SMA

25 MHz SE-to-DS From DPLL Out7p

NAC_OPPS_P/N

SMA

PPS from GPS or 1588

DS-to-SE

SMA

External Sync Clock

NAC_CLK_SYNCED_P/N
ETH_I2C_CLK2 ETH_I2C_DATA2

SyncE Clock Output
from SoC AC Coupled

NAC_TIME_SYNC_P/N
SoC

REF4p REF0n REF3p

OUT3p/n OUT5p/n
OUT6p

REF1p/n

OUT7p

DPLL

REF4n

OSCB

Internal PHY clock for SyncE 1588 Time Sync Clock PLL_INT_N
PPS Output To ICX-D

OCXO

XO

SRC_CLKREQ5_N_GPP_W81

Notes: 1. DS = Differential; SE = Single-ended 2. PPS from GPS and 1588 Eth can be input to DPLL 3. ESD protection needs be considered for SMA header 4. Any unused LVDS signals should be left unconnected

NAC_TIME_REF_P/N NAC_CLKIN_EREF0_P/N
Differential Signal Single-ended Signal

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Figure 75: Synchronous Ethernet Example Implementation

Appendices

SMA 1PPS

156,25 to PV

PHY

RCLK_A/B

SMA GPS 1PPS 1PPS

SDP SDP

5

2 / 3

i225
StoD
Module

NAC_TIME_SYNC INT_N
TIME_REF CLK_EREF0

SoC

CLK_SYNCE0

SDP 0 / 1

SDP 6

DtoS
ON_PPS_OUT

SDP 7

OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9

IN 0 IN 1 IN 2 IN 3 IN 4
XTAL
DPLL

no Stuff
XO OCXO

Table 33: SDP Use in Figure Above

SDP Meaning

Direction Notes

0 Recovered Clock A In

1 Recovered Clock B In

2 Output Clock (+)

Out

3 Output Clock (-)

Out

4

5 1 PPS Out

Out

6 1 PPS In

In

7 1 PPS In (GNSS)

In

In (to Module) Differential Pair on SDP2 and 3

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SyncE Summary
· Provides physical layer synchronization signal over Ethernet  Allows expensive central clock to be shared across the network
· Defined in ITU-T G.8261, G.8262, G.8262.1, and G.8264 specs  G.8261 and G.8262 series define physical layer interface  G.8264 defines messaging channel used to provide pedigree of clock sources
SyncE can be used alone or in conjunction with PTP:

Table 34: SyncE / PTP Matrix

Attribute

SyncE Only

Frequency Accuracy

Yes

Phase Accuracy

No

Time of Day (ToD)

No

PTP Only
Yes Yes Yes

SyncE + PTP
Yes Yes Yes

Appendices

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Appendices

6.2.

Appendix B: Alternative eDP Example

The alternative eDP example presented in Figures 76 through 81 below comes, with permission, from an Intel reference schematic for a late model CORE series processor. Some parts of the example may not be directly relevant to COM-HPC embedded designs in that they dwell on eDP back-light display power supplies and on a display connector used in certain reference platforms. Nonetheless, the materials may be of interest to some readers and are included in this Appendix.

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Figure 76: Alternative eDP Example (Sheet 1 of 6): Passive Stuffing Options ­ eDP and DSI

COM COM COM COM COM COM COM COM

EDP_TX0EDP_TX0+ EDP_TX1EDP_TX1+ EDP_TX2EDP_TX2+ EDP_TX3EDP_TX3+

C7G3 C7G2 C7G1 C7F9 C7F8 C7F7 C7F6 C7F5

1

2

01.1UF X7R2

01.1UF X7R2

01.1UF X7R2

01.1UF X7R2

01.1UF X7R2

01.1UF X7R2

01.1UF X7R2

0.1UF X7R

EDP_TX0_CEDP_TX0_C+ EDP_TX1_CEDP_TX1_C+ EDP_TX2_CEDP_TX2_C+ EDP_TX3_CEDP_TX3_C+

OUT OUT OUT OUT OUT OUT OUT OUT

COM

EDP_AUX-

C7F4

1

2

EDP_AUX_C-

BI

0.1UF X7R

COM

EDP_AUX+

C7F3

1

2

EDP_AUX_C+

BI

0.1UF X7R

A36096-110 0402

AC CAP SHOULD BE REPLACED WITH 0R RESISTOR FOR THE MIPI-DSI DISPLAY

IN

EDP_TX3_C+

H30143-001

R7F20

1

2

0 0% 0.05W EMPTY
0201

EDP_LANE3_MIPI_D3_L+

IN

EDP_TX3_C-

IN

EDP_TX2_C+

4

3

L7F2 90 CHOKE 30% SM_A J16541-001

1

2

H30143-001

R7F21

1

2

0 0% 0201

0.05W EMPTY

H30143-001

R7F22

1

2

0 0% 0.05W EMPTY
0201

EDP_LANE3_MIPI_D3_LEDP_LANE2_MIPI_CLK_L+

4

3

L7F3 90 CHOKE 30% SM_A J16541-001

1

2

IN

EDP_TX2_C-

H30143-001

R7F23

1

2

0 0% 0.05W EMPTY
0201

EDP_LANE2_MIPI_CLK_L-

CAD NOTE: CMC PAD SHARING WITH RESISTOR

IN

EDP_AUX_C+

IN

EDP_AUX_C-

OUT

IN

EDP_TX1_C+

OUT

IN

EDP_TX1_C-

OUT

IN

EDP_TX0_C+

OUT

IN

EDP_TX0_C-

3

H30143-001

R7F18

1

2

0 0%

0.05W RES

0201

EDP_AUX_MIPI_D0_L+

OUT

4

L7F1 90 EMPTY 30% SM_A J16541-001

NEED TO STUFF CMC FOR MDSI

1

EDP_AUX_MIPI_D0_L-

OUT

H30143-001

R7F19

1

2

0 0% 0201 0.05W RES

2

H30143-001

R7F24

1

2

0 0% 0.05W EMPTY
0201

EDP_LANE1_MIPI_D2_L+

OUT

4

3

L7F4 90 CHOKE 30% SM_A J16541-001

1

2

EDP_LANE1_MIPI_D2_L-

OUT

H30143-001

R7F25

1

2

0 0% 0201

0.05W EMPTY

H30143-001

R7G1

1

2

0 0% 0.05W EMPTY
0201

EDP_LANE0_MIPI_D1_L+

OUT

4

3

L7G1 90 CHOKE 30% SM_A J16541-001

1

2

EDP_LANE0_MIPI_D1_L-

OUT

H30143-001

R7G2

1

2

0 0% 0.05W EMPTY
0201

CAD NOTE: CMC PAD SHARING WITH RESISTOR

PICMG® COM-HPC® Carrier Board Design Guide Draft

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Appendices 151/159

Figure 77: Alternative eDP Example (Sheet 2 of 6): Backlight Control Options

BACKLIGHT CONTROL

COM

EDP_BKLTCTL

COM

EDP_BKLT_EN

R7F12 1 0
0402
R3R13 1 0
0402

2
RES
2
EMPTY

EDP_BRIGHTNESS_CONN MIPI1_PWM

R7F15 1 0

2

0402 RES

R3T6 1 0

2

0402 RES

R7E4 1 0 0402

2 EMPTY

R3R4

1 0
0402

2
EMPTY

EDP_BKLT_EN_CONN EDP_BKLT_EN_R MIPI1_BKLTEN_R MIPI1_EN

OUT OUT
OUT OUT OUT OUT

ADDITIONAL AMOLED POWER REQUIREMENTS

+VCC_EDP1_AMOLED1

J7E1 CON HDR_1X3

-V_ELVSS_EDP1_AMOLED1

+VCC_EDP1_AMOLED1

1

JA

2 3

A91829-001

GND

C7F1

1

A36096-112 0.1UF

10%

25V

2

X7R 0402

GND DESIGN NOTE:
THE HEADER JA SHOULD NEVER BE SHORTED WITH JUMPER SHORTING LINK

NORMAL EDP PANEL AMOLED EDP PANEL

STUFF RA & RC RB & RD

UNSTUFF RB & RD RA & RC

-V_ELVSS_EDP1_AMOLED1

R7E1 0.01 0.1 25W

H11304-001 1% EMP2TY

0805

RB

-VSS_EDP1_AMOLED1

R8E1

A93552-004 10

0% 0.1W

RA

2 RES

0603

GND

+VCC_EDP1_BKLT

+VCC_EDP1_BKLT_R

+VCC_EDP1_AMOLED1

RD D71825-002 1 R7F5 2 1%

0.01 0.1W

0603 RES

RC R7F4

1

2

0.01

0603

0.1W 1% EMPTY

COM

EDP_VDD_EN

IN

BUF_PLT_RST#

COM

EDP_HPD

COM GPIO_03

R3T2 R3T1

1 0

2

0402 RES

10

2

0402 EMPTY A93549-001

R7F17

10

2

0402 EMPTY A93549-001

R7F16 R7F11 R7F10

1 0
0402

2
RES

1 0

2

0402 EMPTY A93549-001

1 0

2

0402 EMPTY A93549-001

EDP1_EN_BKLT_SHDN#

OUT

MIPI1_VDD_EN_R

OUT

EDP_HPD_MIPI_PNL_RST_R

IN

PANEL_MDSI_A_TE1

IN

DESIGN NOTE: MAKESURE COMPUTE SIDE IS 1.8V BEFORE ENABLE THIS PATH

+VCC_EDP1_AMOLED1

+V5P5P_MIPI1 +V5P5N_MIPI1
-VSS_EDP1_AMOLED1

R7F9 R7F8 R7F7 R7F6

0.01 1

2 EMPTY

0603 0.1W 1%

0.01D171825-0022 EMPTY

0603 0.1W 1%

0.01D171825-0022 EMPTY

0603 0.1W 1%

0.01D171825-0022 RES

0603 0.1W 1%

D71825-002

+V5P5P_MIPI1_AMOLED1 +V5P5N_MIPI1_AMOLED1

Appendices

PICMG® COM-HPC® Carrier Board Design Guide Draft

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152/159

Appendices

Figure 78: Alternative eDP Example (Sheet 3 of 6): Connector to Display Panel Assembly

J7F1 SCON

+V3P3DX_EDP1_MIPI1

C7G6 602433-081 1 22UF 20% 6.3V 2 X5R 0603 GND +V3P3S

C7G4

1

A36096-112 0.1UF

10%

25V

2

X7R 0402

+VCC_EDP1_BKLT_R

C7F2 602433-081 1 22UF 20% 6.3V 2 X5R 0603

C3T5 602433-081 1 22UF 20% 6.3V 2 X5R 0603

C3T6

1

A36096-112 0.1UF

10%

25V

2

X7R 0402

GND

C3T1

1

A36096-112 0.1UF

10%

25V

2

X7R 0402

GND

+V3P3S

IN IN OUT

EDP_BKLT_EN_CONN EDP_BRIGHTNESS_CONN PANEL_MDSI_A_TE1

R7F14

1

A93549-016 1K

5%

0.0625W 2 EMPTY

0402

DESIGN NOTE:
PIN 20 MDSI_A_TE1 IS 1.8V

R7F13

1

A93549-016 1K

5%

0.0625W 2 EMPTY

0402

OUT DISP_BKLPWM_OUT_MDSI1

IN IN

EDP_LANE0_MIPI_D1_LEDP_LANE0_MIPI_D1_L+

IN IN

EDP_LANE1_MIPI_D2_LEDP_LANE1_MIPI_D2_L+

IN IN

EDP_LANE2_MIPI_CLK_LEDP_LANE2_MIPI_CLK_L+

IN IN

EDP_LANE3_MIPI_D3_LEDP_LANE3_MIPI_D3_L+

BI BI

EDP_AUX_MIPI_D0_LEDP_AUX_MIPI_D0_L+

OUT

EDP_HPD_MIPI_PNL_RST_R

TP_VSYNC_EDP1
+V3P3DX_EDP1_MIPI1 +V3P3S +V1P8_MIPI1

+VCC_MIPI1

+VCC_EDP1_BKLT_R +VCC_MIPI1
+V1P8_MIPI1

+V5P5P_MIPI1_AMOLED1 +V5P5N_MIPI1_AMOLED1
A_DISP0_VLED_FB0 A_DISP0_VLED_FB1 A_DISP0_VLED_FB2 A_DISP0_VLED_FB3 A_DISP0_VLED_FB4 A_DISP0_VLED_FB5

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 IO16 IO17 IO18 IO19 IO20 IO21 IO22 IO23 IO24 IO25 IO26 IO27 IO28 IO29 IO30 IO31 IO32 IO33 IO34 IO35 IO36 IO37 IO38 IO39 IO40 IO41 IO42 IO43 IO44 IO45 IO46 IO47 IO48 IO49 IO50 IO51 IO52 IO53 IO54 IO55 IO56 IO57 IO58 IO59 IO60

C3T2

C3R8

C3R7

602433-081

H48130-001

G21127-001

1 22UF

1 10UF

1 0.1UF

20%

10%

10%

6.3V

GND

25V

50V

2 X5R

2 EMPTY

2 X7R

0603

0805

0402

GND

GND

CON_1X60_27EM

MH1 MH2 MH3 MH4 MH5 MH6 MH7 MH8 MH9 MH10 MH11 MH12 MH13 MH14 MH15 MH16 MH17 MH18 MH19 MH20 MH21 MH22 MH23 MH24 MH25 MH26 MH27

MH1 MH2 MH3 MH4 MH5 MH6 MH7 MH8 MH9 MH10 MH11 MH12 MH13 MH14 MH15 MH16 MH17 MH18 MH19 MH20 MH21 MH22 MH23 MH24 MH25 MH26 MH27

GND

K22036-001

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Appendices

Figure 79: Alternative eDP Example (Sheet 4 of 6): Backlight LED Driver

IN

MIPI1_EN

IN

MIPI1_PWM

IN

DISP_BKLPWM_OUT_MDSI1

+V12_ATX
C7E1 G33975-001 1 10UF 20% 25V 2 X5R 0603 GND

R3R16 0402 10

2 EMPTY

A93549-001

R3R5

1

A93549-027 100K

5%

2

0.0625W RES

0402

GND

C3R4

1

A36096-112 0.1UF

10%

25V

2

EMPTY 0402

GND

R3R8 A93549-085 1 5.1K 5% 0.0625W 2 RES 0402 MIPI1_COMP_19.6_R C3R1 1 22NF 10% 25V 2 X7R 0402 A36096-089
GND

+VCC_MIPI1

R7E3 G22026-041 1 10 1% 0.1W 2 RES 0603

C7E2

1

A36096-112 0.1UF

10%

25V

2

X7R 0402

L7E1 10UH 11.89A
SM

652666-125

20%

IND 2

+VCC_MIPI1_L

MIPI1_VDC

C3R5

1

A36096-112 0.1UF

10%

25V

2

X7R 0402

GND

CR7E1

A

C

MBRS340T3G DIO 3A SM C81983-001

VOUT_OVP = 21V

R3R28 A93549-001 1 0 0% 0.0625W 2 EMPTY 0402 MIPI1_OVP_VOLT1 R3R22 A93548-219 1 154K 1% 0.0625W 2 RES 0402

R3R30 A93549-001 1 0 0% 0.0625W 2 RES 0402 MIPI1_OVP_VOLT2 R3R24 A93548-412 1 165K 1% 0.0625W 2 RES 0402

R3R29 A93549-001 1 0 0% 0.0625W 2 EMPTY 0402 MIPI1_OVP_VOLT3 R3R23 A93548-222 1 174K 1% 0.0625W 2 RES 0402

C3R9 G66843-002 1 4.7UF 10% 25V 2 X7R 1206 GND
VOVP =1.2V

GND

+V12S_MIPI1_R_VIN

MIPI1_COMP MIPI1_ISET MIPI1_FREQ

R3R2 A93548-450 1 12K 1% 0.0625W 2 RES 0402

R3R3 G64084-106 1 22K 1% 0.0625W 2 RES 0402

EU3R1 IC
RT8532

19

VIN

1

EN

17

PWM

20

COMP

3

ISET

2

FREQ

5

AGND

13 14 21

PGND PGND GND

VDC
LX LX
OVP
MIX
LED6 LED5 LED4 LED3 LED2 LED1

G55311-001

18 15 16 12 MIPI1_OVP 4 MIPI1_MIX

R3R1

1

A93549-023 10K

5%

0.0625W 2 RES

0402

GND

R3R21

1

A93548-034 10K

1%

0.0625W 2 RES

0402

GND

C3R6

1

A36095-025 47PF

5%

50V

2

C0G 0402

GND

6 A_DISP0_MIPI1_VLED_FB5_R_TI 7 A_DISP0_MIPI1_VLED_FB4_R_TI 8 A_DISP0_MIPI1_VLED_FB3_R_TI 9 A_DISP0_MIPI1_VLED_FB2_R_TI 10 A_DISP0_MIPI1_VLED_FB1_R_TI 11 A_DISP0_MIPI1_VLED_FB0_R_TI
R3R7 10
0%
2 RES 0402

R3R6 R3R9 R3R11 R3R14 R3R17 R3R25

0402 0402 0402 0402 0402 0402

1 1 1 1 1 1

0 0 0 0 0 0

R3R10 R3R12 R3R15 R3R18 R3R19

1 0 0%

1 0 0%

10 0%

1 0 0%

1 0 0%

2 RES 0402

2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 0402 0402 0402 0402 A93549-001

2 2 2 2 2 2

EMPTY EMPTY RES RES RES RES

A_DISP0_VLED_FB5 A_DISP0_VLED_FB4 A_DISP0_VLED_FB3 A_DISP0_VLED_FB2 A_DISP0_VLED_FB1 A_DISP0_VLED_FB0

CAD NOTE:
3 PAD

OUT OUT OUT OUT OUT OUT

GND

GND

GND

GND

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Figure 80: Alternative eDP Example (Sheet 5 of 6): Split Rail (Pos / Neg) PS for AMOLED

+V3P3_ATX

+V1P8_MIPI1

R8E6 0.01 1

EMPTY

0603

2

+V3P3A_IN_MIPI1

0.1W 1%

D71825-002

R7E2

1

A93549-023 10K

5%

0.0625W 2 RES

0402

V1P8_MIPI1_EN

R8E4 1

2

C8E4

1

A36096-125 10UF

20%

10V

2

X5R 0402

0402 EMPTY 0

GND

1

IN

MIPI1_BKLTEN_R

C8E1 A36096-143 1 1UF 10% 25V 2 X5R 0402
GND

8

+V5_MIPI1_L2

13

2 L8E1

14

G52290-004

2.2UH 0806

1 30% IND 1.2A 15

+V5_MIPI1_L1

16

MIPI1_AUX

4

C8E2

1

A36096-112 0.1UF

10%

25V

2

X7R 0402

5 11 12 17 GND

EU8E1 IC
TPS65135

VIN

OUTP

OUTP

EN

L2

L2

FB

L1 L1
VAUX
GND PGND PGND THPAD

FBG
OUTN OUTN

G84590-001

9 10 7 V5P5_MIPI1_FB 6 V5P5_MIPI1_FBG 2 3

GND

+V3P3_DUAL

R3T3 1

2

0402 RES

MIPI1_VDD_LS_VIN

0

C3T7 1 A36096-112

0.1UF

10%

2

25V X7R

0402

GND

IN

MIPI1_VDD_EN_R

MIPI1_VDD_SR

C3T4

1

A36096-075 2.2NF

10%

50V

2

X7R 0402

GND

+V1P8_A

U3T1 IC SLG7NT402V

1

VDD

2

ON

7

CAP

D

3

S

5

GND

8

C3T3

1

A36096-125 10UF

20%

10V

2

X5R 0402

GND

G54192-001 GND

R8E2

1

A93548-601 365K

1%

0.0625W 2 RES

0402

R8E5 A93548-564 1 107K 1% 0.0625W 2 RES 0402

R8E3

1

G21796-216 475K

1%

0.0625W 2 RES

0402

+V5P5P_MIPI1

C7E3

1

A36096-125 10UF

20%

10V

2

X5R 0402

GND

+V5P5N_MIPI1

C8E3

1

A36096-125 10UF

20%

10V

2

X5R 0402

GND

+V1P8_MIPI1

PICMG® COM-HPC® Carrier Board Design Guide Draft

Rev. 2.1 / (c) Copyright 2021, 2022, 2023 PICMG August 15, 2023

Appendices 155/159

Figure 81: Alternative eDP Example (Sheet 6 of 6): High Side Gate Driver for eDP Backlight

+V5_ATX

R7G6

10 0402

2 RES

VDD_EDP1_BKLT C7G9 A36096-143 1 1UF 10% 25V 2 X5R 0402
GND

EU7G1 IC
SLG55021-200010

1

VCC

D

G

5 7 EDP1_GATE_DRV

IN

EDP_BKLT_EN_R

2

ON

PG

8 TP_EDP1_BKLT_PG

4

GND

SHDN_N

3 EDP1_EN_BKLT_SHDN#

IN

S

6

9

THPAD

GND

G56246-001

+V12_ATX

+VCC_EDP1_BKLT

5
D
4 GS 1 23

Q7G1 MFET
AON6500 J91717-001

+V3P3_ATX

R7G5

10 0402

2 RES

VDD_EDP1_SUPPLY

C7G8

1

A36096-112 0.1UF

10%

25V

2

X7R 0402

GND

IN

EDP1_EN_BKLT_SHDN#

U7G1

IC SLG5NT1458V

1

VDD

CAP

7

2

ON

S

5

3

D

GND

8

V3P3DX_EDP1_SR_CAP

C7G7

1

A36096-075 2.2NF

10%

50V

2

X7R 0402

GND

+V3P3_ATX

H10115-001

GND

C7G5

1

A36096-125 10UF

20%

10V

2

X5R 0402

GND

+V3P3DX_EDP1_MIPI1

PICMG® COM-HPC® Carrier Board Design Guide Draft

Rev. 2.1 / (c) Copyright 2021, 2022, 2023 PICMG August 15, 2023

Appendices 156/159

6.3.

Appendix C: eSPI Header Example

Appendices

Figure 82: eSPI Header Example

ESPI HEADER

+V3P3_A

+V5S

+V1P8_A

+V3P3_A
R9G3 0.1W
R9G4 0.1W

1 0603 1 0603

+V3P3_A_V1P8A_ESPI

2 EMPTY 0 A93552-004 0%

2 RES

0

A93552-004 0%

C9G1

1

A36096-112 0.1UF

10%

25V

2

X7R 0402

GND

IN IN IN
BI

ESPI_CLK_HDR ESPI_CS0_HDR# PLTRST_1P8_ESPI# ESPI_IO3_HDR

BI IN

ESPI_IO0_HDR ESPI_SMB_CLK

DESIGN NOTE:
ALL PU AT COMPUTE MODULE SIDE

IN

BUF_PLT_RST_1.8#

COM

ESPI_ALERT0#

COM

ESPI_ALERT1#

COM

ESPI_CS0#

COM

ESPI_CS1#

COM

ESPI_IO0

COM

ESPI_IO1

COM

ESPI_IO2

COM

ESPI_IO3

COM

ESPI_CLK

COM

ESPI_RST#

R9F3

1

2

0402 RES 0 0% 0.0625W A93549-001

R1U4

1

2

0402 RES 0 0% 0.0625W A93549-001

R9G6

1

2

0402 RES 0 0% 0.0625W A93549-001

R9F2

1

2

0402 RES 0 0% 0.0625W A93549-001

R1U3

1

2

0402 RES 0 0% 0.0625W A93549-001

R9G1

1

2

0402 RES 0 0% 0.0625W A93549-001

R1U1

1

2

0402 RES 0 0% 0.0625W A93549-001

R1T1

1

2

0402 RES 0 0% 0.0625W A93549-001

R9F4

1

2

0402 RES 0 0% 0.0625W A93549-001

R9F1

1

2

0402 RES 0 0% 0.0625W A93549-001

R9G5

1

2

0402 RES 0 0% 0.0625W A93549-001

PLTRST_1P8_ESPI# ESPI_ALERT0_HDR# ESPI_ALERT1_HDR# ESPI_CS0_HDR# ESPI_CS1_HDR# ESPI_IO0_HDR ESPI_IO1_HDR ESPI_IO2_HDR ESPI_IO3_HDR ESPI_CLK_HDR ESPI_RST_HDR#

IN OUT

ESPI_RST_HDR# ESPI_ALERT1_HDR#
+V5_A

C9G2

1

A36096-112 0.1UF

OUT

10% 25V

2

X7R 0402

IN GND

IN

IN

OUT

BI

OUT

BI

BI

BI

BI

OUT

OUT

C9F2

1

A36096-112 0.1UF

10%

25V

2

X7R 0402

GND

J9G1

SCON

HDR_2X14_K4_K21_K22

C9F1

1

A36096-112 0.1UF

10%

25V

2

X7R 0402

1

2

3

5

6

GND

7

8

ESPI_IO2_HDR

9

10

ESPI_IO1_HDR

11

12

BI BI

13 15 17

14

ESPI_SMB_DATA

16

ESPI_CS1_HDR#

18

BI IN

19

20

ESPI_ALERT0_HDR#

OUT

23

24

25

26

27

28

H46981-001

GND

GND

PCIE_X4_G0_SMB_CLK PCIE_X4_G0_SMB_DATA

R9G2

1

2 ESPI_SMB_CLK

0402 RES 0 0% 0.0625W A93549-001

R1U2

1

2 ESPI_SMB_DATA

0402 RES 0 0% 0.0625W A93549-001

OUT BI

PICMG® COM-HPC® Carrier Design Guide

Rev. 2.1 / Aug 10, 2023 157/159

Appendices

6.4.

Appendix D: Useful Books ­ General x86 Computer Topics

Table 35: General Books on x86 Computer Topics

Title

Author

Note

PCI Express System Architecture

Ravi Budruk, Don Anderson, Tom Shanley

www.mindshare.com

PCI System Architecture (4th Edition)

Tom Shanley, Don Anderson

www.mindshare.com

Universal Serial Bus System Architecture

Don Anderson

www.mindshare.com

SATA Storage Technology

Don Anderson

www.mindshare.com

Protected Mode Software Architecture (The PC System Architecture Series)

Tom Shanley

www.mindshare.com

The Unabridged Pentium 4

Tom Shanley

www.mindshare.com

Building the Power-Efficient PC: A Developer's Guide to ACPI Power Management, First Edition

Jerzy Kolinski, Ram Chary, Andrew Intel Press, 2002, ISBN 0-9702846-

Henroid, and Barry Press

8-3

Hardware Bible

Winn L. Rosch

SAMS, 1997, 0-672-30954-8

The Indispensable PC Hardware Book

Hans-Peter Messmer

Addison-Wesley, 1994, ISBN 0-20162424-9

The PC Handbook: For Engineers, Programmers, and Other Se- John P. Choisser and John O. Fos- Annabooks, 1997, ISBN 0-929392-

rious PC Users, Sixth Edition

ter

36-1

PC Hardware in a Nutshell, 3rd Edition

Robert Bruce Thompson and Barbara Fritchman Thompson

O'Reilly, 2003, ISBN 0-596-00513-X

PCI & PCI-X Hardware and Software Architecture & Design, Fifth Edition

Edward Solari and George Willse

Annabooks, Intel Press, 2001, ISBN 0-929392-63-9

PCI System Architecture

Tom Shanley and Don Anderson

Addison-Wesley, 2000, ISBN 0-20130974-2

PCI Express Electrical Interconnect Design: Practical Solutions for Board-level Integration and Validation, First Edition

Dave Coleman, Scott Gardiner, Mo- Intel Press, 2005, hamad Kolberhdari, and Stephen Pe- ISBN 0-9743649-9-1 ters

Introduction to PCI Express: A Hardware and Software Developer's Guide, First Edition

Adam Wilen, Justin Schade, and Ron Thornburg

Intel Press, 2003, ISBN 0-97028469-1

Serial ATA Storage Architecture and Applications, First Edition

Knut Grimsrud and Hubbert Smith

Intel Press, 2003, ISBN 0-97178618-6

USB Design by Example, A Practical Guide to Building I/O De- John Hyde vices, Second Edition

Intel Press, ISBN 0-9702846-5-9

Universal Serial Bus System Architecture, Second Edition

Don Anderson and Dave Dzatko

Mindshare, Inc., ISBN 0-201-309750

Printed Circuits Handbook, Fourth Edition

Clyde F. Coombs Jr.

McGraw-Hill, 1996, ISBN 0--07012754-9

High Speed Signal Propagation, First Edition

Howard Johnson and Martin Graham Prentice Hall, 2003, ISBN 0-13084408-X

High Speed Digital Design: A Handbook of Black Magic, First Edition

Howard Johnson

Prentice Hall, ISBN: 0133957241

C Programmer's Guide to Serial Communications, Second Edi- Joe Campbell tion

SAMS, 1987, ISBN 0-672-22584-0

The Programmer's PC Sourcebook, Second Edition

Thom Hogan

Microsoft Press, 1991, ISBN 155615-321-X

The Undocumented PC, A Programmer's Guide to I/O, CPUs, and Fixed Memory Areas

Frank van Gilluwe

Addison-Wesley, 1997, ISBN 0-20147950-8

VHDL Modeling for Digital Design Synthesis

Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Kluwer Academic Publishers, 1995,

Liu and Eric S. Lin

ISBN: 0-7923-9597-2

PICMG® COM-HPC® Carrier Design Guide

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Appendices

6.5.

Appendix E: Revision History

Table 36: Revision History

Release Interim Date

Rev

Rev

1.0

Mar 17, 2021

RC2.0 Oct 2, 2021

RC2.0a Nov 14, 2021

Author
C. Eder S. Milnor C. Eder S. Milnor C. Eder

RC2.0b RC2.0c RC2.0d

Nov 17, 2021 Dec 6, 2021 Dec 7, 2021

S. Milnor S. Milnor S. Milnor

2.0

Jan 14, 2022

S. Milnor

C. Eder

RC2.1a Apr 29, 2022 S. Milnor

RC2.1b May 11, 2022 S, Milnor RC2.1c Mar 28, 2023 S. Milnor

2.1

August 10, 2023 S. Milnor

C. Eder

Notes / Changes
CDG preliminary version with Ethernet KR and KR4 CEI diagrams.
Release Candidate for first version of complete COM-HPC CDG.
Revise Figure 35 to show a 50V capacitor for C4V20 Revise Figure 41 to show a 50V capacitor for C5W7 Section 3.14.1 Page 96 ­ insert short statement about adding HD Audio support
to pending COM-HPC Base Spec Rev 1.1 due to lack of Soundwire support Remove references to code names for unreleased Intel products ADL and ICL
Revise code name references to show only Intel document numbers
Incorporate nVent Change Requests
Change Rev to RC2.0c, change date, re-issue. No other changes.
Add note to Figure 39 (USB4 ESD diodes) explaining diode positioning Replace Figures 67 and 73 (JSOM diagrams) with revised Figures that call out metric
M2.5 hardware rather than 4-40 Imperial hardware
Formal PICMG release of CDG Revision 2.0
Section 4.3.3 SATA Design Rule Summary Delete erroneous requirements in Ref lines 7 and 8 Renumber Rev 2.0 Ref lines 9, 10, 11, 12 to Rev 2.1 Ref lines 7, 8, 9, 10 Remove TX pair to RX pair length matching requirement (Ref line 9 in in Rev 2.0, Ref line 7 in Rev 2.1)
Section 4.3.4 PCIe Design Rule Summary Remove TX pair to RX pair length matching requirement (Ref line 8) Add missing information on serpentine trace distance to self (Ref line 11)
Updated Figure 8 (CEI Marvel 88E1543 "Alaska" typo) Updated copyright claims to include year 2022 Update Samtec patent claims in Sections 1.71 and 1.72
This is per request from Samtec patent lawyer on 4/25/2022
Section 1.7.2 Page 11 Update Samtec "Unnecessary" patent claims per 3/3/2023 and 3/27/2023 input from Samtec
Section 1.7.4 Page 12 Add year 2023 to Copyright claim Copyright updated to include 2023 in various other parts of the document
Section 1.8 Pages 14 and 13 Correct PCI and PCIe abbreviation explanation ("Interconnect" not "Interface") Fully expand the SATA abbreviation explanation ("Advanced Technology" instead of "AT")
Section 3.6.9 Page 56 Add two PCIe Gen 5 capable redriver parts to Table 9 Section 3.10 Page 88 Correct HPD level translator IC reference from U54 to U49
Formal PICMG release of CDG Revision 2.1 USB4 schematics (Figures 36 through 41) deliberately blurred to satisfy Intel NDA
concerns

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