CYBT-423054-02/CYBT-423060-02, EZ-BT™ WICED Module
"CYBT-423054-02/CYBT-423060-02, EZ-BT™ WICED Module"
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Document DEVICE REPORTInfineon-CYBT-423054-02 CYBT-423060-02 EZ-BT WICED Module-DataSheet-v02 00-ENPlease note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as "Cypress" document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CYBT-423054-02/CYBT-423060-02 EZ-BTTM WICED® Module CYBT-423054-02/CYBT-423060-02, EZ-BTTM WICED® Module General Description The CYBT-423054-02/CYBT-423060-02 are dual-mode Bluetooth BR/EDR and Low Energy wireless module solutions. The CYBT-423054-02 include onboard crystal oscillators, passive components, and the Cypress CYW20719 silicon device. The CYBT-423060-02 includes onboard crystal oscillators, passive components, and the Cypress CYW20721 silicon device. The CYBT-4230xx-02 supports a number of peripheral functions (ADC, PWM), as well as multiple serial communication protocols (UART, SPI, I2C, I2S/PCM). The CYBT-4230xx-02 includes a royalty-free Bluetooth LE stack compatible with Bluetooth 5.0 in a small 11.0 × 11.0 × 1.70 mm module form-factor. The CYBT-4230xx-02 includes an integrated chip antenna, is qualified by Bluetooth SIG, and includes regulatory certification approval for FCC, ISED, MIC, and CE. Module Description Functional Capabilities Module size: 11.00 mm × 11.00 mm × 1.70 mm Complies with Bluetooth Core Specification version 5.0 and includes support for BR, EDR 2/3 Mbps, eSCO, Bluetooth LE, and LE 2 Mbps features. QDID: 152533 Declaration ID: D050854 Certified to FCC, ISED, MIC, and CE standards 1024-KB flash memory, 512-KB SRAM memory Industrial temperature range: 30 °C to +85 °C Integrated Arm Cortex-M4 microprocessor core with floating point unit (FPU) RF Characteristics Maximum TX output power: +4.0 dbm RX Receive Sensitivity: 95.5 dbm Received signal strength indicator (RSSI) with 1-dB resolution Power Consumption TX current consumption Bluetooth silicon: 5.6 mA (MCU + radio only, 0 dbm) RX current consumption Bluetooth silicon: 5.9 mA (MCU + radio only) Cypress CYW20719/21 silicon low power mode support PDS: 6.1 µA with 512 KB SRAM retention SDS: 1.6 µA HIDOFF (External Interrupt): 400 nA 1x ADC with (10-bit ENoB for DC measurement and 12-bit ENoB for Audio measurement) with 11 channels. 1x HCI UART for programming and HCI 1x peripheral UART (PUART) 2x SPI (master or slave mode) blocks (SPI, Quad SPI, and MIPI DBI-C) 1x I2C master/slave and 1x I2C master only I2S/PCM audio interfaces Up to six 16-bit PWMs Watchdog Timer (WDT) Bluetooth Basic Rate (BR) and Enhanced Data Rate (EDR) Support Bluetooth LE protocol stack supporting generic access profile (GAP) Central, Peripheral, or Broadcaster roles Hardware Security Engine Benefits CYBT-4230xx-02 is fully integrated and certified solution that provides all necessary components required to operate Bluetooth communication standards. Proven hardware design ready to use Ultra-flexible supermux I/O designs allows maximum flexibility for GPIO function assignment Large nonvolatile memory for complex application devel- opment Over-the-Air (OTA) update capable for development or field updates Bluetooth SIG qualified with QDID and Declaration ID WICEDTM Studio provides an easy-to-use integrated design environment (IDE) to configure, develop, program, and test your Bluetooth application Cypress Semiconductor Corporation · 198 Champion Court Document Number: 002-30912 Rev. *A · San Jose, CA 95134-1709 · 408-943-2600 Revised December 17, 2020 CYBT-423054-02/CYBT-423060-02 More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. References Overview: EZ-BLE/EZ-BT Module Portfolio, Module Roadmap Development Kits: CYBT-423028-EVAL, CYBT-423028-02 Evaluation Board CYW920719Q40EVB-01, Evaluation Kit for CYW20719 silicon device Test and Debug Tools: CYSmart, Bluetooth® LE Test and Debug Tool (Windows) CYSmart Mobile, Bluetooth® LE Test and Debug Tool (Android/iOS Mobile App) Knowledge Base Article KBA97095 - EZ-BLETM Module Placement KBA223751 - RF Regulatory Certifications for CYBT-423028-02, CYBT-423054-02 and CYBT-423060-02 EZ-BTTM WICED Modules KBA213976 - FAQ for BLE and Regulatory Certifications with EZ-BLE modules KBA210802 - Queries on BLE Qualification and Declaration Processes KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules KBA223428 - Programming an EZ-BT WICED Module KBA225450 - Putting 2073x, 2070x, and 20719 Based Devices or Modules in HCI Mode Development Environments Wireless Connectivity for Embedded Devices (WICED) Studio Software Development Kit (SDK) Cypress' WICED® (Wireless Connectivity for Embedded Devices) is a full-featured platform with proven Software Development Kits (SDKs) and turnkey hardware solutions from partners to readily enable Wi-Fi and Bluetooth® connectivity in system design. WICED Studio is the only SDK for the Internet of Things (IoT) that combines Wi-Fi and Bluetooth into a single integrated development environment. In addition to providing WICED APIs and an application framework designed to abstract complexity, WICED Studio also leverages many common industry standards. Technical Support Cypress Community: Whether you're a customer, partner or a developer interested in the latest Cypress innovations, the Cypress Developer Community offers you a place to learn, share and engage with both Cypress experts and other embedded engineers around the world. Frequently Asked Questions (FAQs): Learn more about our Bluetooth ECO System. Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt. Document Number: 002-30912 Rev. *A Page 2 of 48 CYBT-423054-02/CYBT-423060-02 Contents Overview ............................................................................ 4 Functional Block Diagram ........................................... 4 Module Description ...................................................... 4 Pad Connection Interface ................................................ 6 Recommended Host PCB Layout ................................... 7 Module Connections ........................................................ 9 Connections and Optional External Components ..... 11 Power Connections (VDD) ........................................ 11 External Reset (XRES) .............................................. 12 HCI UART Connections ............................................ 12 External Component Recommendation .................... 12 Critical Components List ........................................... 14 Antenna Design ......................................................... 14 Bluetooth Baseband Core ............................................. 15 BQB and Regulatory Testing Support ....................... 15 Power Management Unit ................................................ 16 Integrated Radio Transceiver ........................................ 17 Transmitter Path ........................................................ 17 Receiver Path ............................................................ 17 Local Oscillator .......................................................... 17 Microcontroller Unit ....................................................... 18 External Reset ........................................................... 18 Peripheral and Communication Interfaces .................. 19 I2C ............................................................................. 19 HCI UART Interface .................................................. 19 Peripheral UART Interface ........................................ 19 Serial Peripheral Interface ......................................... 19 32 kHz Crystal Oscillator ........................................... 20 ADC Port ................................................................... 21 GPIO Ports ................................................................ 21 PWM .......................................................................... 22 PDM Microphone ....................................................... 23 I2S Interface .............................................................. 23 PCM Interface ........................................................... 23 Security Engine ......................................................... 24 Power Modes .................................................................. 25 Firmware .......................................................................... 25 Electrical Characteristics ............................................... 26 Core Buck Regulator ................................................. 28 Digital LDO ................................................................ 29 Digital I/O Characteristics .......................................... 29 ADC Electrical Characteristics .................................. 30 Chipset RF Specifications ............................................. 31 Timing and AC Characteristics ..................................... 34 UART Timing ............................................................. 34 SPI Timing ................................................................. 34 I2C Compatible Interface Timing ............................... 36 Environmental Specifications ....................................... 39 Environmental Compliance ....................................... 39 RF Certification .......................................................... 39 Safety Certification .................................................... 39 Environmental Conditions ......................................... 39 ESD and EMI Protection ........................................... 39 Regulatory Information .................................................. 40 FCC ........................................................................... 40 ISED .......................................................................... 41 European Declaration of Conformity ......................... 42 MIC Japan ................................................................. 42 Packaging ........................................................................ 43 Ordering Information ...................................................... 45 Acronyms ........................................................................ 46 Document Conventions ................................................. 46 Units of Measure ....................................................... 46 Document History Page ................................................. 47 Sales, Solutions, and Legal Information ...................... 48 Worldwide Sales and Design Support ....................... 48 Products .................................................................... 48 PSoC® Solutions ....................................................... 48 Cypress Developer Community ................................. 48 Technical Support ..................................................... 48 Document Number: 002-30912 Rev. *A Page 3 of 48 CYBT-423054-02/CYBT-423060-02 Overview Functional Block Diagram Figure 1 illustrates the CYBT-4230xx-02 functional block diagram. Figure 1. Functional Block Diagram CYW20719/21 Note General Purpose Input/Output pins shown in Figure 1 are configurable to any specified input or output function in the SuperMux table detailed in Table 5 in the Module Connections section. Note Connections shown in the above block diagram are maximum number of connections per function. The total number of GPIOs available on the CYBT-4230xx-02 is 17. Module Description The CYBT-4230xx-02 module is a complete module designed to be soldered to the applications main board. Module Dimensions and Drawing Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections will still guarantee that all mechanical specifications and module certifications are maintained. Any changes to the current BOM for the CYBT-4230xx-02 will not be made until approval is provided by the end customer for this product. The CYBT-4230xx-02 will be held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm). Table 1. Module Design Dimensions Module dimensions Dimension Item Antenna location dimensions PCB thickness Shield height Maximum component height Total module thickness (bottom of module to top of shield) Length (X) Width (Y) Length (X) Width (Y) Height (H) Height (H) Height (H) Height (H) Specification 11.00 ± 0.15 mm 11.00 ± 0.15 mm 6.00 mm 2.50 mm 0.50 ± 0.10 mm 1.20 mm 0.60 mm typical 1.70 mm typical See Figure 2 for the mechanical reference drawing for CYBT-4230xx-02. Document Number: 002-30912 Rev. *A Page 4 of 48 CYBT-423054-02/CYBT-423060-02 Figure 2. Module Mechanical Drawing Top View (See from Top) Side View Bottom View (Seen from Bottom) Note 1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see "Recommended Host PCB Layout" on page 7. Document Number: 002-30912 Rev. *A Page 5 of 48 CYBT-423054-02/CYBT-423060-02 Pad Connection Interface As shown in the bottom view of Figure 2 on page 5, the CYBT-4230xx-02 has 28 connections to a host board via solder pads (SP). Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-4230xx-02 module. Table 2. Connection Description Name Connections SP 28 Connection Type Solder Pad Pad Length Dimension Pad Width Dimension 0.86 mm 0.51 mm Pad Pitch 0.91 mm Figure 3. Solder Pad Dimensions (Seen from Bottom) Solder Pad Connections (Seen from Bottom) To maximize RF performance, the host layout should follow these recommendations: 1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) must contain no ground or signal traces. This keep out area requirement applies to all layers of the host board. 2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the chip antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 3 below. Refer to AN96841 for module placement best practices. 3. Optional Keepout: To maximize RF performance, the area immediately around the Cypress Bluetooth module chip antenna may contain an additional keep out area, where there are no grounding or signal traces. The keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm). Figure 4. Optional Additional Host PCB Keep Out Area Around the CYBT-4230xx-02 Chip Antenna Optional Host PCB Keep Out Area Around Chip Antenna (Seen from Bottom) Document Number: 002-30912 Rev. *A Page 6 of 48 CYBT-423054-02/CYBT-423060-02 Recommended Host PCB Layout Figure 5, Figure 6, Figure 7, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBT-4230xx-02. Dimensions are in millimeters unless otherwise noted. Pad length of 1.11 mm (0.56 mm from center of the pad on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern. Figure 5. CYBT-4230xx-02 Host Layout (Dimensioned) Figure 6. CYBT-4230xx-02 Host Layout (Relative to Origin) Top View (Seen on Host PCB) Top View (Seen on Host PCB) Document Number: 002-30912 Rev. *A Page 7 of 48 CYBT-423054-02/CYBT-423060-02 Table 3 provides the center location for each solder pad on the CYBT-4230xx-02. All dimensions are referenced to the center of the solder pad. Refer to Figure 7 for the location of each module solder pad. Table 3. Module Solder Pad Location Figure 7. Solder Pad Reference Location Solder Pad (Center of Pad) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Location (X,Y) from Dimension from Orign (mm) Orign (mils) (0.31, 2.79) (12.20, 109.84) (0.31, 3.71) (12.20, 146.06) (0.31, 4.62) (12.20, 181.89) (0.31, 5.54) (12.20, 218.11) (0.31, 6.45) (12.20, 253.94) (0.31, 7.37) (12.20, 290.16) (0.31, 8.28) (12.20, 325.98) (0.31, 9.19) (12.20, 361.81) (0.31, 10.11) (12.20, 398.03) (1.39,10.69) (54.72, 420.87) (2.30,10.69) (90.55, 420.87) (3.21,10.69) (126.38, 420.87) (4.13,10.69) (162.60, 420.87) (5.04,10.69) (198.42, 420.87) (5.96,10.69) (234.65, 420.87) (6.87,10.69) (270.47, 420.87) (7.79,10.69) (306.69, 420.87) (8.70,10.69) (342.52, 420.87) (9.61,10.69) (378.35, 420.87) (10.69,10.11) (420.87, 398.03) (10.69,9.19) (420.87, 361.81) (10.69,8.28) (420.87, 325.98) (10.69,7.37) (420.87, 290.16) (10.69,6.45) (420.87, 253.94) (10.69,5.54) (420.87, 218.11) (10.69,4.62) (420.87, 181.89) (10.69,3.71) (420.87, 146.06) (10.69,2.79) (420.87, 109.84) Top View (Seen on Host PCB) Document Number: 002-30912 Rev. *A Page 8 of 48 CYBT-423054-02/CYBT-423060-02 Module Connections Table 4 details the solder pad connection definitions and available functions for each connection pad. The GPIO connections available on the CYBT-4230xx-02 can be configured to any of the input or output functions listed in Table 5. Table 4 specifies any function that is required to be used on a specific solder pad, and also identifies GPIOs that can be configured using the SuperMux. Table 4. CYBT-4230xx-02 Solder Pad Connection Definitions Pad Pad Name Silicon Pin Name 1 GND GND XTAL I/O ADC GPIO Ground SuperMux Capable[2] 2 HOST_WAKE BT_HOST_WAKE A signal from the CYBT-4230xx-02 module to the host indicating that the Bluetooth device requires attention. 3 UART_RXD BT_UART_RXD UART (HCI UART) Receive Data Only 4 UART_TXD BT_UART_TXD UART (HCI UART) Transmit Data Only 5 UART_RTS_N BT_UART_RTS_N UART (HCI UART) Request To Send Output Only 6 UART_CTS_N BT_UART_CTS_N UART (HCI UART) Clear To Send Input Only 7 P2 P2 - - see Table 5 8 VCC VDDIO Power Supply Input (1.76V ~ 3.63V) 9 P6 P6 - - see Table 5 10 GND GND Ground 11 XRES RST_N External Reset (Active Low) 12 P33 P33 - IN6 see Table 5 13 P25 P25 - - see Table 5 14 P26 P26 - - see Table 5 15 P38 P38 - IN1 see Table 5 P34 16 P34/P35/P36 P35 P36 IN5 (P34) - IN4 (P35) (P34/P35/P36) see Table 5 IN3 (P36) 17 P1 P1 - IN28 see Table 5 18 P0 P0 - IN29 see Table 5 19 P29 P29 - IN10 see Table 5 P13 20 P13/P23/P28 P23 P28 IN22 (P13) - IN12 (P23) (P13/P23/P28) see Table 5 IN11 (P28) 21 P10/P11 P10 P11 - IN25 (P10) IN24 (P11) (P10/P11) see Table 5 22 P17 P17 - IN18 see Table 5 23 P7 P7 - - - 24 P4 P4 - - - 25 P16 P16 - IN19 - 26 XTALI_32K/ P15[3] XTALI_32K P15 External Oscillator Input (32kHz) IN20 (P15) (P15) (P15), see Table 5 27 XTALO_32K XTALO_32K External Oscillator Output (32kHz) - - - 28 GND GND Ground Notes 2. The CYBT-423054-02/CYBT-423060-02 can configure GPIO connections to any Input/Output function described in Table 5. 3. P15 should not be driven high externally while the part is held in reset (it can be floating or driven low). Failure to do so may cause some current to flow through P15 until the device comes out of reset. Document Number: 002-30912 Rev. *A Page 9 of 48 CYBT-423054-02/CYBT-423060-02 Table 5 details the available Input and Output functions that are configurable to any solder pad in Table 4 which are marked as SuperMux capable. Table 5. GPIO SuperMux Input and Output Functions Function SPI 1 SPI 2 PUART I2C PCM In PCM Out I2S In I2S Out PDM Input/Output Function Type GPIOs Required Input/Output Serial Communication (Master or Slave) Output 4 ~ 8 Input/Output Serial Communication (Master or Slave) 4 ~ 8 Output Input Serial Communication Input 4 Output Serial Communication Output Input/Output Serial Communication (Master or Slave) 2 Input Audio Input Communication 3 Output Audio Output Communication 3 Input Audio Input Communication 3 Output Input Audio Output Communication Microphone 3 1 ~ 2 Function Connection Description SPI 1 Clock SPI 1 Chip Select SPI 1 MOSI SPI 1 MISO SPI 1 I/O 2 (Quad SPI) SPI 1 I/O 3 (Quad SPI) SPI 1 Interrupt SPI 1 DCX (DBI-C DCX 8-bit mode) SPI 2 Clock SPI 2 Chip Select SPI 2 MOSI SPI 2 MISO SPI 2 I/O 2 (Quad SPI) SPI 2 I/O 3 (Quad SPI) SPI 2 Interrupt SPI 2 DCX (DBI-C DCX 8-bit mode) Peripheral UART RX Peripheral UART CTS Peripheral UART TX Peripheral UART RTS I2C Clock I2C Data PCM Input PCM Clock PCM Sync PCM Output PCM Clock PCM Sync I2S DI, Data Input I2S WS, Word Select I2S Clock I2S DO, Data Output I2S WS, Word Select I2S Clock PDM Input Channel 1 PDM Input Channel 2 Document Number: 002-30912 Rev. *A Page 10 of 48 CYBT-423054-02/CYBT-423060-02 Table 5. GPIO SuperMux Input and Output Functions (continued) Function Input/Output Function Type GPIOs Required PWM Output Pulse Width Modulator 1 ~ 6 Function Connection Description PWM Channel 0 PWM Channel 1 PWM Channel 2 PWM Channel 3 PWM Channel 4 PWM Channel 5 Connections and Optional External Components Power Connections (VDD) The CYBT-4230xx-02 contains one power supply connection, VDD. VDD accepts a supply input of 1.76 V to 3.63 V. Table 12 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Table 12. Considerations and Optional Components for Brownout (BO) Conditions Power supply design must be completed to ensure that the CYBT-4230xx-02 module does not encounter a Brownout condition, which can lead to unexpected functionality, or module lock up. A Brownout condition may be met if power supply provided to the module during power up or reset is in the range shown below: VILVDD VIH. Refer to Table 17 for the VIL and VIH specifications. System design should ensure that the condition above is not encountered when power is removed from the system. In the event this cannot be guaranteed (i.e., battery installation, high value power capacitors with slow discharge), it is recommended that an external voltage detection device be used to prevent the Brownout voltage range from occurring during power removal. Refer to Figure 8 for the recommended circuit design when using an external voltage detection IC. Figure 8. Reference Circuit Block Diagram for External Voltage Detection IC In the event that the module does encounter a Brownout condition, and is operating erratically or not responsive, power cycling the module will correct this issue and once reset, the module should operate correctly. Brownout conditions can potentially cause issues that cannot be corrected, but in general, a power-on reset (POR) operation will correct a Brownout condition. Document Number: 002-30912 Rev. *A Page 11 of 48 CYBT-423054-02/CYBT-423060-02 External Reset (XRES) The CYBT-4230xx-02 has an integrated POR circuit which completely resets all circuits to a known power on state. This action can also be invoked by an external reset signal, forcing it into a POR state. The XRES signal is an active-low signal, which is an input to the CYBT-4230xx-02 module (solder pad 11). The CYBT-4230xx-02 module does not require an external pull-up resistor on the XRES input. During power on operation, the XRES connection to the CYBT-4230xx-02 is required to be held low 50 ms after the VDD power supply input to the module is stable. This can be accomplished in the following ways: The host device can connect a GPIO to the XRES of Cypress CYBT-4230xx-02 module and pull XRES low until VDD is stable. XRES is recommended to be released 50 ms after VDD is stable. If the XRES connection of the CYBT-4230xx-02 module is not used in the application, a 0.33 µF capacitor may be connected to the XRES solder pad of the CYBT-4230xx-02 in order to delay the XRES release. The capacitor value for this recommended implementation is approximate, and the exact value may differ depending on the VDD power supply ramp time of the system. The capacitor value should result in an XRES release timing of at least 50 ms after VDD stability. The XRES release timing may be controlled by a external voltage detection IC. XRES should be released 50 ms after VDD is stable. Refer to Figure 11 on page 18 for XRES operating and timing requirements during power on events. HCI UART Connections The recommendations in this section apply to the HCI UART (Solder Pads 3, 4, 5, and 6). For full UART functionality, all UART signals must be connected to the Host device. If full UART functionality is not being used, and only UART RXD and TXD are desired or capable, then the following connection considerations should be followed for UART RTS and CTS: UART RTS: Can be left floating, pulled low, or pulled high. RTS is not critical for initial firmware uploading at power on. UART CTS: Must be pulled low to bypass flow control and to ensure that continuous data transfers are made from the host to the module. External Component Recommendation Power Supply Circuitry It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead between the supply and the module connection can be included. The ferrite bead should be positioned as close as possible to the module pad connection. If used, the recommended ferrite bead value is 330 , 100 MHz. (Murata BLM21PG331SN1D). Document Number: 002-30912 Rev. *A Page 12 of 48 CYBT-423054-02/CYBT-423060-02 Figure 9 illustrates the CYBT-4230xx-02 schematic. Figure 9. CYBT-4230xx-02 Schematic Diagram P10/P11 VCC P17 P7 P6 P4 P2 P16 XTALI_32K/P15 XTALO_32K TP8 TP1 TP10 TP28 TP11 TP6 TP5 TP3 TP4 TP18 TP17 TP7 TP24 TP9 TP23 TP21 TP25 TP22 TP13 TP14 TP20 TP19 TP12 TP16 TP15 TP26 TP27 TP2 VCC XRES UART_CTS_N UART_RTS_N UART_RXD UART_TXD P0 P1 P2 P4 P6 P7 P10/P11 P16 P17 P25 P26 P13/P23/P28 P29 P33 P34/P35/P36 P38 XTALI_32K/P15 XTALO_32K HOST_WAKE MODULE CMYBOTD-4U23L0E28-02 U1 CUY1W20719B1 CYBT-423054-02 CYW20719B2 CYBT-423060-02 CYW20721B2 U1 33 32 31 P4 34 40 39 38 37 36 35 41 P2 P16 XTALI_32K/P15 XTALO_32K GND P10/P11 LHL_VDDO P17 P7 P6 Pin 1 is For Radiator Electrode Pin 3 is For Feeding A1 1 3 LC1 3.9nH,0201 LC5 LC2 5.6nH,0201 Antenna LC3 0.5pF,0201 LC4 1.8pF,0201 2.7nH,0201 P13/P23/P28 1 P29 2 P0 3 P1 4 P34/P35/P36 5 P38 6 P26 7 P25 8 P33 9 XRES 10 P13/P23/P28 P29 P0 P1 P34/P35/P36 P38 P26 P25 P33 RST_N CYW20719/20721 18 BT_RF DIGLDO_VDDIN PAVDD 16 RFLDO_VDDIN JTAG_SEL SR_VLX SR_VDDBAT3V RFLDO_VDDOOUT LC6 1.8pF,0201 17 11 12 13 14 15 19 21 IFVDD1P2 PLLVDD1P2 20 VCOVDD1P2 UART_CTS_N UART_RTS_N UART_TXD UART_RXD BT_VDDC BT_VDDO HOST_WAKE XTALO XTALI 30 29 28 27 26 25 24 23 22 QFN40 UART_CTS_N UART_RTS_N UART_TXD UART_RXD HOST_WAKE VCC Y1 24.000MHz Antenna Matching Filter CBUCK_OUT L1 2.2uH,0603 C3 1.0uF,0201 1 3 C1 12pF,0201 4 2 C2 12pF,0201 VCC RFLDO_OUT CBUCK_OUT RFLDO_OUT IF/PLL_1P2 VCO_1P2 P29 2 P0 P1 P34/P35/P36 P38 P26 P25 P33 XRES GND 19 20 P13/P23/P28 P10/P11 P17 P7 P4 P16 XTALI_32K/P15 XTALO_32K 28 GND 10 P6 9 VCC P2 UART_CTS_N UART_RTS_N UART_TXD UART_RXD HOST_WAKE GND 1 VCC C5 10uF,0402 PIN13 C7 0.1uF,0201 PIN25 C9 0.1uF,0201 PIN39 CBUCK_OUT C10 1.0uF,0201 PIN15 RFLDO_OUT IF/PLL_1P2 FB1 600@100M FB2 600@100M VCO_1P2 C4 0.1uF,0201 C6 0.1uF,0201 C8 10pF,0201 RFLDO_OUT C11 2.2uF,0402 PIN14 C12 1.0uF,0201 PIN17 MODULE PAD ASSIGNMENT (BOTTOM VIEW) Cypress Semiconductor Corp. Title CYBT-423028/423054/423060 Size Document Number B 630 20114 01 Document Number: 002-30912 Rev. *A Page 13 of 48 CYBT-423054-02/CYBT-423060-02 Critical Components List Table 6 details the critical components used in the CYBT-4230xx-02 module. Table 6. Critical Component List Component Silicon Reference Designator Description U2 40-pin QFN Bluetooth Silicon Device - CYW20719/21 Chip Antenna A1 Antenna, 2.4 GHz Crystal Y1 24 MHz, 8 pF Antenna Design Table 7 details the chip antenna used in the CYBT-4230xx-02 module. Table 7. Chip Antenna Specifications Item Frequency Range 2400 2500 MHz Peak Gain -1.0 dBi typical Return Loss 10.0 dB typical Description Document Number: 002-30912 Rev. *A Page 14 of 48 CYBT-423054-02/CYBT-423060-02 Bluetooth Baseband Core The Bluetooth Baseband Core (BBC) implements all time-critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It prioritizes and schedules all RX/TX activities including adv, paging, scanning, and servicing of connections. In addition to these functions, it independently handles the host controller interface (HCI) including all commands, events, and data flowing over HCI. The core also handles symbol timing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), authentication, data encryption/decryption, and data whitening/dewhitening. Table 8. Bluetooth Features Bluetooth 1.0 Basic Rate SCO Paging and Inquiry Page and Inquiry Scan Sniff Bluetooth 2.1 Secure Simple Pairing Enhanced Inquiry Response Sniff Subrating Bluetooth 4.1 Low Duty Cycle Advertising Dual Mode LE Link Layer Topology Bluetooth 1.2 Interlaced Scans Adaptive Frequency Hopping eSCO Bluetooth 3.0 Unicast Connectionless Data Enhanced Power Control eSCO Bluetooth 4.2 Data Packet Length Extension LE Secure Connection Link Layer Privacy Bluetooth 2.0 EDR 2 Mbps and 3 Mbps Bluetooth 4.0 Bluetooth Low Energy Bluetooth 5.0 LE 2 Mbps Slot Availability Mask High Duty Cycle Advertising BQB and Regulatory Testing Support The CYBT-4230xx-02 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loop back tests, and reduced hopping sequence. In addition to the standard Bluetooth Test Mode, the CYBT-4230xx-02 also supports enhanced testing features to simplify RF debugging and qualification and type-approval testing. These features include: Fixed frequency carrier wave (unmodulated) transmission Simplifies some type-approval measurements (Japan) Aids in transmitter performance analysis Fixed frequency constant receiver mode Receiver output directed to I/O pin Allows for direct BER measurements using standard RF test equipment Facilitates spurious emissions testing for receive mode Fixed frequency constant transmission 8-bit fixed pattern or PRBS-9 Enables modulated signal measurements with standard RF test equipment Document Number: 002-30912 Rev. *A Page 15 of 48 CYBT-423054-02/CYBT-423060-02 Power Management Unit Figure 10 shows the CYW20719/21 power management unit (PMU) block diagram. The CYW20719/21 includes an integrated buck regulator, a bypass LDO, a capless LDO for digital circuits and a separate LDO for RF. The bypass LDO automatically takes over from the buck once Vbat supply falls below 2.1 V. The voltage levels shown in this figure are the default settings; the firmware may change voltage levels based on operating conditions. Figure 10. Default Usage Mode CYW20719/21 PMU Document Number: 002-30912 Rev. *A Page 16 of 48 CYBT-423054-02/CYBT-423060-02 Integrated Radio Transceiver The CYBT-4230xx-02 has an integrated radio transceiver that has been designed to provide low power operation in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with Bluetooth Radio Specification 3.0 and meets or exceeds the requirements to provide the highest communication link quality of service. Transmitter Path CYBT-4230xx-02 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band. Digital Modulator The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal. Power Amplifier The CYBT-4230xx-02 has an integrated power amplifier (PA) that can transmit up to +4 dBm for class 2 operation. Receiver Path The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, and an extended dynamic range to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the CYBT-4230xx-02 to be used in most applications without off-chip filtering. Digital Demodulator and Bit Synchronizer The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm. Receiver Signal Strength Indicator The radio portion of the CYBT-4230xx-02 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power. Local Oscillator The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The CYBT-4230xx-02 uses an internal loop filter. Document Number: 002-30912 Rev. *A Page 17 of 48 CYBT-423054-02/CYBT-423060-02 Microcontroller Unit The CYBT-4230xx-02 includes a Arm Cortex-M4 processor with 2 MB of ROM, 448 KB of data RAM, 64 KB of patch RAM, and 1 MB of on-chip flash. The CM4 has a maximum speed of 96 MHz. CYBT-4230xx-02 supports execution from on-chip flash (OCF). The CM4 also includes a single precision IEEE 754 compliant floating point unit (FPU). The CM4 runs all the BT layers as well as application code. The ROM includes LM, HCI, L2CAP, GATT, as well as other stack layers freeing up the flash for application usage. A standard serial wire debug (SWD) interface provides debugging support. External Reset An external active-low reset signal, XRES, can be used to put the CYBT-4230xx-02 in the reset state. An external voltage detector reset IC with 50 ms delay is recommended on the XRES connection. The XRES must only be released after the VDDO supply voltage level has been stabilized for 50 ms. Figure 11. Reset Timing Document Number: 002-30912 Rev. *A Page 18 of 48 CYBT-423054-02/CYBT-423060-02 Peripheral and Communication Interfaces I2C The CYBT-4230xx-02 provides a 2-pin I2C compatible master interface to communicate with I2C compatible peripherals. The following transfer clock rates are supported: 100 kHz 400 kHz 800 kHz (Not a standard I2C-compatible speed) 1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed) SCL and SDA lines can be routed to any of the P0-P39 GPIOs allowing for flexible system configuration. When used as SCL/SDA, the GPIOs go into open drain mode and require an external pull-up for proper operation. I2C block does not support multi master capability by either master or slave devices. I2C is Master Only. HCI UART Interface The CYBT-4230xx-02 includes a UART interface for factory programming as well as when operating as a BT HCI device in a system with an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 115200 bps to 1.5 Mbps. Typical rates are 115200, 921600, 1500000 bps although intermediate speeds are also available. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command. The CYBT-4230xx-02 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%. The UART interface has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud. The CYBT-4230xx-02 can wake up the host as needed or allow the host to sleep via the HOST_WAKE signal (solder pad 2). Signal allows the CYBT-4230xx-02 to optimize system power consumption by allowing a host device to remain in low power modes as long as possible. The HOST_WAKE signal can be enabled via a vendor specific command. Peripheral UART Interface The CYBT-4230xx-02 has a second UART that may be used to interface to peripherals. This peripheral UART is accessed through the optional I/O ports, which can be configured individually and separately for each functional pin. The CYBT-4230xx-02 can map the peripheral UART to any GPIO. The Peripheral UART functionality is the same as the HCI UART, but with a 256-byte transmit and receive FIFO. Serial Peripheral Interface The CYBT-4230xx-02 has two independent SPI interfaces. Both interfaces support Single, Dual, and Quad mode SPI operations as well as MIPI DBI-C Interface. Either of the interface can be a master or a slave. SPI2 can support only one slave. SPI1 has a 1024 byte transmit and receive buffers which is shared with the host UART interface. SPI2 has a dedicated 256 byte transmit and receive buffers. To support more flexibility for user applications, the CYBT-4230xx-02 has optional I/O ports that can be configured individually and separately for each functional pin. SPI IO voltage depends on VDDO. MIPI Interface There are three options in DBI type-C corresponding to 9-bit, 16-bit, and 8-bit modes. The CYBT-4230xx-02 plays the role of host, and only the 9-bit and 8-bit modes (option 1 and option 3 in DBI-C spec) are supported. In the 9-bit mode, the SCL, CS, MOSI, and MISO pins are used. In the 8-bit mode, an additional pin (DCX) is required. The DCX pin indicates if the current outgoing bit stream is a command or data byte. Document Number: 002-30912 Rev. *A Page 19 of 48 CYBT-423054-02/CYBT-423060-02 32 kHz Crystal Oscillator The CYBT-4230xx-02 utilizes the built-in Local Oscillator (LO) on the CYW20719/21 silicon device for 32 kHz timing. The accuracy of the LO is +/- 500 ppm. The use of an external XTAL oscillator is optional. CYBT-4230xx-02 includes external XTAL oscillator connections for applications requiring higher timing accuracy. Figure 12 shows an external 32 kHz XTAL oscillator with external components and Table 9 lists the recommended external oscillator's characteristics. This oscillator input can be operated with a 32 kHz or 32.768 kHz crystal oscillator or be driven with a clock input at similar frequency. The default component values are: R1 = 10 M and C1 = C2 = ~6 pF. The values of C1 and C2 are used to fine-tune the oscillator. Figure 12. 32 kHz Oscillator Block Diagram Table 9. XTAL Oscillator Characteristics Parameter Symbol Output frequency Frequency tolerance Foscout Start-up time Tstartup XTAL drive level Pdrv XTAL series resistance Rseries XTAL shunt capacitance Cshunt External AC input amplitude VIN (AC) Conditions Crystal-dependent For crystal selection For crystal selection For crystal selection Ccouple = 100 pF; Rbias= 10 M Min Typ Max 32.768 100 500 0.5 70 2.2 400 Unit kHz ppm ms µW k pF mVpp Document Number: 002-30912 Rev. *A Page 20 of 48 CYBT-423054-02/CYBT-423060-02 ADC Port The ADC is a - ADC core designed for audio (13 bits) and DC (10 bits) measurement. It operates at 12 MHz and has 11 solder pad connections that can act as input channels. The internal bandgap reference has ±5% accuracy without calibration. Calibration and digital correction schemes can be applied to reduce ADC absolute error and improve measurement accuracy in DC mode. The following CYBT-4230xx-02 module solder pads can be used as ADC inputs: Pad 12: P33, ADC Input Channel 6 Pad 15: P38, ADC Input Channel 1 Pad 16: P34/P35/P36, ADC Input Channels 5/4/3 respectively. Note Only one ADC input on this solder pad can be active at a given time. Pad 17: P1, ADC Input Channel 28 Pad 18: P0, ADC Input Channel 29 Pad 19: P29, ADC Input Channel 10 Pad 20: P13/P23/28, ADC Input Channels 22/12/11 respectively. Note Only one ADC input on this solder pad can be active at a given time. Pad 21: P10/P11, ADC Input Channels 25/24 respectively. Note Only one ADC input on this solder pad can be active at a given time. Pad 22: P17, ADC Input Channel 18 Pad 25: P16, ADC Input Channel 19 Pad 26: P15, ADC Input Channel 20 GPIO Ports The CYBT-4230xx-02 has a maximum of 17 general-purpose I/Os (GPIOs). All GPIOs support the following: Programmable pull-up/down of approximately 45 k. Input disable, allowing pins to be left floating or analog signals connected without risk of leakage. Source/sink 8 mA at 3.3V and 4 mA at 1.8V. P15 is Bonded to the same pin as XTALI_32K (Pad 26). If an External 32.768 kHz crystal is not used, then this pin can be used as GPIO P15. P26/P28/P29 can sink/source 16 mA at 3.3V and 8 mA at 1.8V. Most peripheral functions can be assigned to any GPIO. For details, refer to Table 5 on page 10. For more details on SuperMux configuration and control, refer to "SuperMux Wizard for CYW20719" user guide. The list below details the GPIOs that are available on the CYBT-4230xx-02 module: P0-P2, P4, P6, P7, P16, P17, P25, P26, P29, P33, and P38 P10/P11 (Double bonded connection on the CYBT-4230xx-02 module, only one of two is available) P13/P23/P28 (Triple bonded connection on the CYBT-4230xx-02 module, only one of three is available) P15/XTALI_32K (Double bonded pin on the CYBT-4230xx-02 module, only one of two is available) P34/P35/P36 (Triple bonded pin on the CYBT-4230xx-02 module, only one of three is available) P19, P20, and P39 are reserved for system use. Do not use these three GPIOs. For GPIOs highlighted as double or triple bonded connections, only one of the connections can be used at a given time. When a certain GPIO is selected, the other GPIOs bonded to the same connection must be configured to input with output disable. Document Number: 002-30912 Rev. *A Page 21 of 48 CYBT-423054-02/CYBT-423060-02 PWM The CYBT-4230xx-02 has six internal PWMs, labeled PWM0-5. The PWM module consists of the following: Each of the six PWM channels contains the following registers: 16-bit initial value register (read/write) 16-bit toggle register (read/write) 16-bit PWM counter value register (read) PWM configuration register shared among PWM05 (read/write). This 18-bit register is used: To configure each PWM channel To select the clock of each PWM channel To change the phase of each PWM channel The application can access the PWM module through the FW driver. Figure 13 shows the structure of one PWM channel. Figure 13. PWM Block Diagram Document Number: 002-30912 Rev. *A Page 22 of 48 CYBT-423054-02/CYBT-423060-02 PDM Microphone The CYBT-4230xx-02 accepts a -based one-bit pulse density modulation (PDM) input stream and outputs filtered samples at either 8 kHz or 16 kHz sampling rates. The PDM signal derives from an external kit that can process analog microphone signals and generate digital signals. The PDM input shares the filter path with the auxADC. Two types of data rates can be supported: 8 kHz 16 kHz The external digital microphone takes in a 2.4 MHz clock generated by the CYBT-4230xx-02 and outputs a PDM signal which is registered by the PDM interface with either the rising or falling edge of the 2.4 MHz clock selectable through a programmable control bit. The design can accommodate two simultaneous PDM input channels, so stereo voice is possible. Note Subject to the driver support in WICED Studio. I2S Interface The CYBT-4230xx-02 supports a single I2S digital audio port. with both master and slave modes. The I2S signals are: I2S Clock: I2S SCK I2S Word Select: I2S WS I2S Data Out: I2S DO I2S Data In: I2S DI I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S DO always stays as an output. The channel word length is 16 bits and the data is justified so that the MSN of the left-channel data is aligned with the MSB of the I2S bus, per I2S Specifications. The MSB of each data word is transmitted one bit clock cycle after the I2S WS transition, synchronous with the falling edge of bit clock. Left Channel data is transmitted when I2S WS is low, and right-channel data is transmitted when I2S WS is high. Data bits sent by the CYBT-4230xx-02 are synchronized with the falling edge of I2S SCK and should be sampled by the receiver on the rising edge of the I2S SCK. Note The PCM interface shares HW with the I2S interface and only one can be used at a given time. PCM Interface The CYBT-4230xx-02 includes a PCM interface that can connect to linear PCM codec devices in master or slave mode. In master mode, the CYBT-4230xx-02 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYBT-4230xx-02. The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands. Note The PCM interface shares HW with the I2S interface and only one can be used at a given time. Slot Mapping The CYBT-4230xx-02 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM Interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or 1024 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot. Frame Synchronization The CYBT-4230xx-02 supports both short- and long-frame synchronization in both master and slave modes. In short frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCGM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot. Data Formatting The CYBT-4230xx-02 may be configured to generate and accept several different data formats. For conventional narrow band speech mode, the CYBT-4230xx-02 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2's complement data, left justified, and clocked MSB first. Document Number: 002-30912 Rev. *A Page 23 of 48 CYBT-423054-02/CYBT-423060-02 Burst PCM Mode In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with an HCI command from the host. Security Engine The CYBT-4230xx-02 includes a hardware security accelerator which greatly decreases the time required to perform typical security operations. Access to the hardware block is provided via a firmware interface. This security engine includes: Public key acceleration (PKA) cryptography AES-CTR/CBC-MAC/CCM acceleration SHA2 message hash and HMAC acceleration RSA encryption and decryption of modulus sizes up to 2048 bits Elliptic curve Diffie-Hellman in prime field GF(p) Note Security Engine is used only by the Bluetooth stack to reduce CPU overhead. It is not available for application use. Random Number Generator This hardware block is used for key generation for Bluetooth. Note Availability for use by the application is subject to the support in WICED Studio. Note The Random Number Generator block must be warmed up prior to use. A delay of 500 ms from cold boot is necessary prior to using the Random Number Generator. Document Number: 002-30912 Rev. *A Page 24 of 48 CYBT-423054-02/CYBT-423060-02 Power Modes The CYBT-4230xx-02 support the following HW power modes are supported: Active mode - Normal operating mode in which all peripherals are available and the CPU is active. Idle mode - In this mode, the CPU is in "Wait for Interrupt" (WFI) and the HCLK, which is the high frequency clock derived from the main crystal oscillator is running at a lower clock speed. Other clocks are active and the state of the entire chip is retained. Sleep mode - In this mode, CPU is in WFI and the HCLK is not running. The PMU determines if the other clocks can be turned off and does accordingly. State of the entire chip is retained, the internal LDOs run at a lower voltage (voltage is managed by the PMU), and SRAM is retained. PDS mode - This mode is an extension of the PMU Sleep wherein most of the peripherals such as UART and SPI are turned off. The entire memory is retained, and on wakeup the execution resumes from where it paused. Shut Down Sleep (SDS) - Everything is turned off except the IO Power Domain, RTC, and LPO. The device can come out of this mode either due to BT activity or by an external interrupt. Before going into this mode, the application can store some bytes of data into "Always On RAM" (AON). When the device comes out of this mode, the data from AON is restored. After waking from SDS, the application will start from the beginning (warmboot) and has to restore its state based on information stored in AON. In the SDS mode, a single BT task with no data activity, such as an ACL connection, Bluetooth LE connection, or Bluetooth LE advertisement can be performed. HIDOFF (Timed-Wake) mode - The device can enter this mode asynchronously, that is, the application can force the device into this mode at any time. IO Power Domain, RTC, and LPO are the only active blocks. A timer that runs off the LPO is used to wake the device up after a predetermined fixed time. HIDOFF (External Interrupt-Waked) mode - This mode is similar to Timed-Wake, but in HID-off mode even the LPO and RTC are turned off. So, the only wakeup source is an external interrupt. Transition between power modes is handled by the on-chip firmware with host/application involvement. See the Firmware Section for details. Firmware The CYBT-4230xx-02 ROM firmware runs on a real time operating system and handles the programming and configuration of all on-chip hardware functions as well as the BT/LE baseband, LM, HCI, GATT, ATT, L2CAP and SDP layers. The ROM also includes drivers for on-chip peripherals as well as handling on-chip power management functions including transitions between different power modes. The CYBT-4230xx-02 is fully supported by the Cypress WICED Studio platform. WICED releases provide latest ROM patches, drivers, and sample applications allowing customized applications using the CYBT-4230xx-02 to be built quickly and efficiently. Refer to WICED Technical Brief and CYBT-4230xx-02 Product Guide for details on the firmware architecture, driver documentation, power modes and how to write applications/profiles using the CYBT-4230xx-02. Document Number: 002-30912 Rev. *A Page 25 of 48 CYBT-423054-02/CYBT-423060-02 Electrical Characteristics The absolute maximum ratings in the following table indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. Table 10. Silicon Absolute Maximum Ratings Requirement Parameter Maximum Junction Temperature VDD IO VDD RF VDDBAT3V DIGLDO_VDDIN1P5 RFLDO_VDDIN1P5 PALDO_VDDIN_5V MIC_AVDD Specification Unit Min Nom Max 125 °C 0.5 3.795 V 0.5 1.38 V 0.5 3.795 V 0.5 1.65 V 0.5 1.65 V 0.5 3.795 V 0.5 3.795 V Table 11. ESD/Latch-up Requirement Parameter ESD Tolerance HBM (Silicon) ESD Tolerance CDM (Silicon) Latch-up Specification Unit Min Nom Max 2000 2000 V 500 500 V 200 mA Table 12. Power Supply Specifications Parameter Conditions Min Typ Max Unit VDD Input Module Input 1.76 3.0 3.63 V VDD Ripple Module Input 100 mV VBAT Input Internal to Module (not accessible) 1.90 3.0 3.6 V PMU Turn-on Time VBAT is ready 300 µs The CYBT-4230xx-02 uses an onboard low voltage detector to shut down the part when supply voltage (VDD) drops below operating range. Table 13. Power Supply Shut Down Specifications VSHUT Parameter Min Typ 1.625 1.7 Max Unit 1.76 V Document Number: 002-30912 Rev. *A Page 26 of 48 CYBT-423054-02/CYBT-423060-02 Table 14. Bluetooth, Bluetooth LE, BR, and EDR Current Consumption Parameter Description Silicon or Module Typ Unit Parameter HCI 48 MHz with Pause Silicon 1.1 mA HCI 48 MHz without Pause Silicon 2.2 mA RX Continuous RX Silicon 5.9 mA TX Continuous TX - 0 dBm Silicon 5.6 mA PDS Silicon 6.1 µA HID-Off (SDS) 32 kHz XTAL and 16 KB Retention RAM on Silicon 1.6 µA Advertising Unconnectable - 1 second Silicon 14 µA Advertising Connectable Undirected - 1 second Silicon 17 µA Page Scan - PDS Interlaced - R1 Silicon 122 µA Sniff - PDS 500 ms Sniff, 1 attempt, 0 timeout - Master Silicon 132 µA Sniff - PDS 500 ms Sniff, 1 attempt, 0 timeout - Slave Silicon 138 µA Bidirectional Data Exchange Continuous DM5 or DH5 packets - Master or Slave Silicon 6.9 mA Bluetooth Low Energy (0 dBm) RX Peak Peak RX current Module 8.8 mA TX Peak Peak TX Current Module 11.2 mA PDS Module 6.9 µA HID-Off (SDS) Module 5.9 µA Advertising - SDS Connectable Undirected - 1 second Module 36 µA LE Connection - SDS Slave - 1 second Module 26 µA Bluetooth Classic (BR, EDR, 0 dBm) IDLE Module is idle, non-discoverable and non-connectable Module 4 µA Iscan Inquiry scan (1.28 seconds) Module 135 µA Pscan Page scan (1.28 seconds) Module 135 µA IScan+Pscan Inquiry scan + Page Scan (1.28 seconds) Module 320 µA Connected Connected with no data transfer Module 4.52 mA Connected + Pscan Connected with no data transfer + Page Scan (1.28 seconds) Module 4.56 mA Connected + IScan + Pscan Connected with no data transfer + Inquiry Scan (1.28 seconds) + Page Scan (1.28 seconds) Module 4.62 mA Connected + SNIFF Connected with no data transfer + SNIFF (500 ms) Module 2.1 mA Connected + SNIFF+ IScan+ Connected with no data transfer + SNIFF (500 ms) Pscan + Inquiry Scan and Page Scan 1.28 seconds Module 2.15 mA TX_BR Data transfer @115200 baud rate Module 9.2 mA TX+SNIFF_BR Data transfer @115200 baud rate + Sniff (500 ms) Module 4.1 mA Document Number: 002-30912 Rev. *A Page 27 of 48 CYBT-423054-02/CYBT-423060-02 Core Buck Regulator Table 15. Silicon Core Buck Regulator Parameter Conditions Min. Typ. Max. Unit Input supply voltage DC, VBAT CBUCK output current DC voltage range inclusive of disturbances LPOM only 1.90 3.0 3.63 V 65 mA Output voltage range Programmable, 30 mV/step default = 1.2 V (bits = 0000) 1.2 1.26 1.5 V Output voltage DC accuracy LPOM efficiency (high load) Includes load and line regulation 4 +4 % 85 % LPOM efficiency (low load) 80 % Input supply voltage ramp-up time 0 to 3.3 V 40 µs Minimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature, and aging. Maximum capacitor value refers to the total capacitance seen at a node where the capacitor is connected. This also includes any decoupling capacitors connected at the load side, if any. Document Number: 002-30912 Rev. *A Page 28 of 48 CYBT-423054-02/CYBT-423060-02 Digital LDO Table 16. Digital LDO Parameter Input supply voltage, Vin Nominal output voltage, Vo Dropout voltage Conditions Min. Typ. Max. Unit Minimum Vin = Vo + 0.12V requirement must be 1.2 1.2 1.6 V met under maximum load. Internal default setting 1.1 V At maximum load 120 mV Digital I/O Characteristics Table 17. Digital I/O Characteristics Characteristics Input low voltage (VDD = 3V) Input high voltage (VDD = 3V) Input low voltage (VDD = 1.8V) Input high voltage (VDD = 1.8V) Output low voltage Output high voltage Input low current Input high current Output low current (VDD = 3 V, VOL = 0.5 V) Output low current (VDD = 1.8 V, VOL = 0.5 V) Output high current (VDD = 3 V, VOH = 2.55 V) Output high current (VDD = 1.8 V, VOH = 1.35 V) Input capacitance Symbol VIL VIH VIL VIH VOL VOH IIL IIH IOL IOL IOH IOH CIN Minimum Typical Maximum Unit 0.8 V 2.4 V 0.4 V 1.4 V 0.45 V VDDO 0.45 V V 1.0 µA 1.0 µA 8.0 mA 4.0 mA 8.0 mA 4.0 mA 0.4 pF Document Number: 002-30912 Rev. *A Page 29 of 48 CYBT-423054-02/CYBT-423060-02 ADC Electrical Characteristics Table 18. Electrical Characteristics Parameter Symbol Conditions/Comments Min Typ Max Current consumption Power down current ITOT At room temperature 2 3 1 ADC Core Specification ADC reference voltage ADC sampling clock VREF From BG with ±3% accuracy 0.85 12 Absolute error Includes gain error, offset and 5 distortion. Without factory calibration. Includes gain error, offset and 2 distortion. After factory calibration. ENOB For audio application 12 13 For static measurement 10 ADC input full scale FS For audio application 1.6 For static measurement 1.8 3.6 Conversion rate For audio application 8 16 For static measurement 50 100 Signal bandwidth For audio application 20 8K For static measurement DC Input impedance RIN For audio application For static measurement 10 500 Startup time For audio application 10 For static measurement 20 MIC PGA Specifications MIC PGA gain range 0 42 MIC PGA gain step 1 MIC PGA gain error Includes part-to-part gain variation 1 1 PGA input referred noise At 42 dB PGA gain A-weighted 4 Passband gain flatness PGA and ADC, 100 Hz4 kHz 0.5 0.5 MIC Bias Specifications MIC bias output voltage At 2.5V supply 2.1 MIC bias loading current 3 MIC bias noise Refers to PGA input 20 Hz to 8 kHz, A-weighted 3 MIC bias PSRR at 1 kHz 40 ADC SNR A-weighted 0 dB PGA gain 78 ADC THD + N 3 dBFS input 0 dB PGA gain 74 GPIO input voltage GPIO source impedance[4] Always lower than avddBAT Resistance 3.6 1 Capacitance 10 Note 4. Conditional requirement for the measurement time of 10 µs. Relaxed with longer measurement time for each GPIO input channel. Unit mA µA V MHz % % Bit kHz Hz KW ms µs dB dB dB µV dB V mA µV dB dB dB V k pF Document Number: 002-30912 Rev. *A Page 30 of 48 CYBT-423054-02/CYBT-423060-02 Chipset RF Specifications Table 19 and Table 20 apply to single-ended industrial temperatures. Unused inputs are left open. Table 19. Chipset Receiver RF Specifications Parameter Mode and Conditions Min Typ Max Unit Frequency range RX sensitivity[5] GFSK, 0.1% BER, 1 Mbps /4-DQPSK, 0.01% BER, 2 Mbps 8-DPSK, 0.01% BER, 3 Mbps 2402 92.0[5] 94.0[6] 88.0[6] 2480 MHz dBm dBm dBm Maximum input All data rates 20 dBm GFSK Modulation C/I cochannel GFSK, 0.1% BER[7] C/I 1 MHz adjacent channel GFSK, 0.1% BER[8] C/I 2 MHz adjacent channel GFSK, 0.1% BER[7] C/I 3 MHz adjacent channel GFSK, 0.1% BER[9] C/I image channel GFSK, 0.1% BER[7] C/I 1 MHz adjacent to image channel GFSK, 0.1% BER[7] 11.0 dB 0 dB 30.0 dB 40.0 dB 9.0 dB 20.0 dB QPSK Modulation C/I cochannel /4-DQPSK, 0.1% BER[7] C/I 1 MHz adjacent channel /4-DQPSK, 0.1% BER[8] C/I 2 MHz adjacent channel /4-DQPSK, 0.1% BER[7] C/I 3 MHz adjacent channel /4-DQPSK, 0.1% BER[9] C/I image channel /4-DQPSK, 0.1% BER[7] C/I 1 MHz adjacent to image channel /4-DQPSK, 0.1% BER[7] 13.0 dB 0 dB 30.0 dB 40.0 dB 9.0 dB 20.0 dB 8PSK Modulation C/I cochannel 8-DPSK, 0.1% BER[7] C/I 1 MHz adjacent channel 8-DPSK, 0.1% BER[7] C/I 2 MHz adjacent channel 8-DPSK, 0.1% BER[7] C/I 3 MHz adjacent channel 8-DPSK, 0.1% BER[9] C/I image channel 8-DPSK, 0.1% BER[7] C/I 1 MHz adjacent to image channel 8-DPSK, 0.1% BER[7] Out-of-Band Blocking Performance (CW)[8] 21.0 dB 5.0 dB 25.0 dB 33.0 dB 0 dB 13 dB 30 MHz to 2000 MHz BDR GFSK 0.1% BER 10.0 dBm 2000 MHz to 2399 MHz BDR GFSK 0.1% BER 27.0 dBm 2498 MHz to 3000 MHz BDR GFSK 0.1% BER 27.0 dBm 3000 MHz to 12.75 GHz BDR GFSK 0.1% BER Inter-modulation Performance[10] 10.0 dBm BT, interferer signal level BDR GFSK 0.1% BER 39.0 dBm Spurious Emissions 30 MHz to 1 GHz 57.0 dBm 1 GHz to 12.75 GHz 55.0 dBm Notes 5. Dirty TX is Off. 6. Up to 1 dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations. 7. The receiver sensitivity is measured at BER of 0.1% on the device interface. 8. Desired signal is 10 dB above the reference sensitivity level (defined as 70 dBm). 9. Desired signal is 3 dB above the reference sensitivity level (defined as 70 dBm). 10. Desired signal is -64 dBm Bluetooth-modulated signal, interferer 1 is 39 dBm sine wave at frequency f1, interferer 2 is 39 dBm Bluetooth modulated signal at frequency f2, f0 = 2 * f1 f2, and |f2 f1| = n * 1 MHz, where n is 3, 4, or 5. For the typical case, n = 4. Document Number: 002-30912 Rev. *A Page 31 of 48 Table 20. Chipset Transmitter RF Specifications Parameter Transmitter Section Frequency range Class 2: GFSK TX power Class 2: EDR TX Power 20 dB bandwidth Adjacent Channel Power |M N| = 2 |M N| 3 Out-of-Band Spurious Emission 30 MHz to 1 GHz 1 GHz to 12.75 GHz 1.8 GHz to 1.9 GHz 5.15 GHz to 5.3 GHz LO Performance Initial carrier frequency tolerance Frequency Drift DH1 packet DH3 packet DH5 packet Drift rate Frequency Deviation Average deviation in payload (sequence used is 00001111) Maximum deviation in payload (sequence used is 10101010) Channel spacing Modulation Accuracy /4-DQPSK Frequency Stability /4-DQPSK RMS DEVM /4-QPSK Peak DEVM /4-DQPSK 99% DEVM 8-DPSK frequency stability 8-DPSK RMS DEVM 8-DPSK Peak DEVM 8-DPSK 99% DEVM In-Band Spurious Emissions 1.0 MHz < |M N| < 1.5 MHz 1.5 MHz < |M N| < 2.5 MHz |M N| > 2.5 MHz CYBT-423054-02/CYBT-423060-02 Min Typ Max Unit 2402 2480 MHz 4.0 dBm 0 dBm 930 1000 kHz 20 dBm 40 dBm 36.0 dBm 30.0 dBm 47.0 dBm 47.0 dBm 75 +75 kHz 25 +25 kHz 40 +40 kHz 40 +40 kHz 20 20 kHz/50 µs 140 175 kHz 115 kHz 1 MHz 10 10 10 kHz 20 % 35 % 30 % 10 kHz 13 % 25 % 20 % 26 dBm 20 dBm 40 dBm Document Number: 002-30912 Rev. *A Page 32 of 48 CYBT-423054-02/CYBT-423060-02 Table 21. Bluetooth LE RF Specifications Parameter Conditions Min Typ Frequency range RX sensitivity (QFN)[11] RX sensitivity (WLCSP)[11] N/A LE GFSK, 0.1% BER, 1 Mbps LE GFSK, 0.1% BER, 1 Mbps 2402 95.0[12] 94.5[12] TX power N/A 4.0 Mod Char: Delta F1 average N/A Mod Char: Delta F2 max[13] N/A 225 255 99.9 Mod Char: Ratio N/A 0.8 0.95 Notes 11. Dirty TX is Off. 12. Up to 1 dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations. 13. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz. Max 2480 275 MHz dBm dBm dBm kHz % % Table 22. CYBT-423054-02/CYBT-423060-02 GPS and GLONASS Band Spurious Emission Parameter 1570-1580 MHz 1592-1610 MHz GPS GLONASS Condition Min Typ 160 159 Max Unit dBm/Hz dBm/Hz Document Number: 002-30912 Rev. *A Page 33 of 48 CYBT-423054-02/CYBT-423060-02 Timing and AC Characteristics In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams. UART Timing Table 23. UART Timing Specifications Reference Characteristics 1 Delay time, UART_CTS_N low to UART_TXD valid. 2 Setup time, UART_CTS_N high before midpoint of stop bit. 3 Delay time, midpoint of stop bit to UART_RTS_N high. Min Typ Max Unit 1.50 Bit periods 0.67 Bit periods 1.33 Bit periods Figure 14. UART Timing SPI Timing The SPI interface can be clocked up to 24 MHz. Table 24 and Figure 15 show the timing requirements when operating in SPI Mode 0 and 2. Table 24. SPI Mode 0 and 2 Reference Characteristics Min Typ Max 1 Time from master assert SPI_CSN to first clock edge 45 ns 2 Hold time for MOSI data lines 12 ½ SCK ns 3 Time from last sample on MOSI/MISO to slave deassert SPI_INT 0 100 ns 4 Time from slave deassert SPI_INT to master deassert SPI_CSN 0 ns 5 Idle time between subsequent SPI transactions 1 SCK ns Document Number: 002-30912 Rev. *A Page 34 of 48 CYBT-423054-02/CYBT-423060-02 Figure 15. SPI Timing, Mode 0 and 2 Table 25 and Figure 16 show the timing requirements when operating in SPI Mode 1 and 3. Table 25. SPI Mode 1 and 3 Reference 1 2 3 4 5 Characteristics Time from master assert SPI_CSN to first clock edge Hold time for MOSI data lines Time from last sample on MOSI/MISO to slave deassert SPI_INT Time from slave deassert SPI_INT to master deassert SPI_CSN Idle time between subsequent SPI transactions Min Typ Max 45 ns 12 ½ SCK ns 0 100 ns 0 ns 1 SCK ns Figure 16. SPI Timing, Mode 1 and 3 Document Number: 002-30912 Rev. *A Page 35 of 48 CYBT-423054-02/CYBT-423060-02 I2C Compatible Interface Timing The specifications in Table 26 references Figure 17. Table 26. I2C Compatible Interface Timing Specifications (up to 1 MHz) Reference Characteristics 1 Clock frequency 2 START condition setup time 3 START condition hold time 4 Clock low time 5 Clock high time 6 Data input hold time[14] 7 Data input setup time 8 STOP condition setup time 9 Output valid from clock 10 Bus free time[15] Min Max Unit 100 400 kHz 800 1000 650 ns 280 ns 650 ns 280 ns 0 ns 100 ns 280 ns 400 ns 650 ns Notes 14. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 15. Time that the CBUS must be free before a new transaction can start. Figure 17. I2C Interface Timing Diagram Document Number: 002-30912 Rev. *A Page 36 of 48 CYBT-423054-02/CYBT-423060-02 Table 27. Timing for I2S Transmitters and Receivers Transmitter Receiver Parameter Lower Limit Upper Limit Lower Limit Upper Limit Notes Min Max Min Max Min Max Min Max Clock Period T Ttr Tr Note 16 Master Mode: Clock generated by transmitter or receiver HIGH tHC 0.35Ttr 0.35Ttr Note 17 LOW tLC 0.35Ttr 0.35Ttr Note 17 Slave Mode: Clock accepted by transmitter or receiver HIGH tHC 0.35Ttr 0.35Ttr Note 18 LOW tLC 0.35Ttr 0.35Ttr Note 18 Rise time tRC 0.15Ttr Note 19 Transmitter Delay tdtr Hold time thtr Receiver 0.8T Note 20 0 Note 19 Setup time tsr 0.2Ttr Note 21 Hold time thr 0.2Ttr Note 21 Notes 16. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer rate. 17. At all data rates respect to T. in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and tLC are specified with 18. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used. 19. BttRReCCciawsuhnsicoehttmhmeoerdaeenltsahyathn(ttrdtRbtr)eCcamonamdx,etwhsehzemereraoxtRiomCr umnmaexgtiarsatinnvosemt. lTeithtseesrrteshpfaoenree0d, .t1(hd5eeTfttirrna.endsmbyittTetrr)haarse related, a fast transmitter driven by a to guarantee that thtr is greater than slow clock or equal to edge zero, csaonlorensgualtsinthtdetrcnlooct kexrciseee-dtiminge 20. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time. 21. The data setup and hold time must not be less than the specified receiver setup and hold time. Document Number: 002-30912 Rev. *A Page 37 of 48 CYBT-423054-02/CYBT-423060-02 Figure 18. I2S Transmitter Timing Figure 19. I2S Receiver Timing Document Number: 002-30912 Rev. *A Page 38 of 48 CYBT-423054-02/CYBT-423060-02 Environmental Specifications Environmental Compliance This Cypress Bluetooth LE module is produced in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen-Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant. RF Certification The CYBT-4230xx-02 module is certified under the following RF certification standards: FCC: WAP3028 ISED: 7922A-3028 MIC: 203-JN0834 CE Safety Certification The CYBT-4230xx-02 module complies with the following safety regulations: Underwriters Laboratories, Inc. (UL): Filing E331901 CSA TUV Environmental Conditions Table 28 describes the operating and storage conditions for the Cypress Bluetooth LE module. Table 28. Environmental Conditions for CYBT-423054-02/CYBT-423060-02 Description Operating temperature Operating humidity (relative, non-condensation) Min Specification 30 °C 5% Thermal ramp rate Storage temperature 40 °C Storage temperature and humidity ESD: Module integrated into system Components[22] Max Specification 85 °C 85% 10 °C/minute 85 °C 85 °C at 85% 15 kV Air 2.0 kV Contact ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability. Note 22. This does not apply to the RF pins (ANT). Document Number: 002-30912 Rev. *A Page 39 of 48 CYBT-423054-02/CYBT-423060-02 Regulatory Information FCC FCC NOTICE: The device CYBT-4230xx-02 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. CAUTION: The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that FCC labeling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP3028. In any case the end product must be labeled exterior with "Contains FCC ID: WAP3028". ANTENNA WARNING: This device is tested with a standard SMA connector and with the antenna listed in Table 7 on page 14. When integrated in the OEMs product, this fixed antenna requires installation preventing end-users from replacing them with non-approved antennas. Any antenna not in Table 7 must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. RF EXPOSURE: To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas in Table 7, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. The radiated output power of CYBT-4230xx-02 with the integrated PCB trace antenna (FCC ID: WAP3028) is far below the FCC radio frequency exposure limits. Nevertheless, use CYBT-4230xx-02 in such a manner that minimizes the potential for human contact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. Document Number: 002-30912 Rev. *A Page 40 of 48 CYBT-423054-02/CYBT-423060-02 ISED Innovation, Science and Economic Development (ISED) Canada Certification CYBT-4230xx-02 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development (ISED) Canada. License: IC: 7922A-3028 Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. This device has been designed to operate with the antennas listed in Table 7 on page 14, having a maximum gain of -0.5 dBi. Antennas not included in Table 7 or having a gain greater than -0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 . The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. ISED NOTICE: The device CYBT-4230xx-02 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. L'appareil CYBT-4230xx-02, y compris l'antenne intégrée, est conforme aux Règles RSS-GEN de Canada. L'appareil répond aux exigences d'approbation de l'émetteur modulaire tel que décrit dans RSS-GEN. L'opération est soumise aux deux conditions suivantes: (1) Cet appareil ne doit pas causer d'interférences nuisibles, et (2) Cet appareil doit accepter toute interférence reçue, y compris les interférences pouvant entraîner un fonctionnement indésirable. ISED INTERFERENCE STATEMENT FOR CANADA This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Cet appareil est conforme à la norme sur l'innovation, la science et le développement économique (ISED) norme RSS exempte de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. ISED RADIATION EXPOSURE STATEMENT FOR CANADA This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. Cet équipement est conforme aux limites d'exposition aux radiations ISED prévues pour un environnement incontrôlé. LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the ISED Notices above. The IC identifier is 7922A-3028. In any case, the end product must be labeled in its exterior with "Contains IC: 7922A-3028". Le fabricant d'équipement d'origine (OEM) doit s'assurer que les exigences d'étiquetage ISED sont respectées. Cela comprend une étiquette clairement visible à l'extérieur de l'enceinte OEM spécifiant l'identifiant Cypress Semiconductor IC approprié pour ce produit ainsi que l'avis ISED ci-dessus. L'identificateur IC est 7922A-3028. En tout cas, le produit final doit être étiqueté dans son extérieur avec "Contient IC: 7922A-3028". Document Number: 002-30912 Rev. *A Page 41 of 48 CYBT-423054-02/CYBT-423060-02 European Declaration of Conformity Hereby, Cypress Semiconductor declares that the Bluetooth module CYBT-4230xx-02 complies with the essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows: All versions of the CYBT-4230xx-02 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. MIC Japan CYBT-4230xx-02 is certified as a module with certification number 203-JN0834. End products that integrate CYBT-4230xx-02 do not need additional MIC Japan certification for the end product. End product can display the certification label of the embedded module. Model Name: EZ-BT WICED Module Part Number: CYBT-423054-02, CYBT-423060-02 Manufactured by Cypress Semiconductor. 203-JN0834 Document Number: 002-30912 Rev. *A Page 42 of 48 CYBT-423054-02/CYBT-423060-02 Packaging Table 29. Solder Reflow Peak Temperature Module Part Number CYBT-423054-02 CYBT-423060-02 Package 28-pad SMT 28-pad SMT Maximum Peak Temperature Maximum Time at Peak Temperature Maximum No. of Cycles 260 °C 30 seconds 2 260 °C 30 seconds 2 Table 30. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Module Part Number CYBT-423054-02 CYBT-423060-02 Package 28-pad SMT 28-pad SMT MSL MSL 3 MSL 3 CYBT-4230xx-02 is offered in tape and reel packaging. Figure 20 details the tape dimensions used for CYBT-4230xx-02. Figure 20. CYBT-4230xx-02 Tape Dimensions Figure 21 details the orientation of the CYBT-4230xx-02 in the tape as well as the direction for unreeling. Figure 21. Component Orientation in Tape and Unreeling Direction Document Number: 002-30912 Rev. *A Page 43 of 48 CYBT-423054-02/CYBT-423060-02 Figure 22 details reel dimensions used for CYBT-4230xx-02. Figure 22. Reel Dimensions CYBT-4230xx-02 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for CYBT-4230xx-02 is detailed in Figure 23. Figure 23. CYBT-4230xx-02 Center of Mass Document Number: 002-30912 Rev. *A Top View (Seen from Top) Page 44 of 48 CYBT-423054-02/CYBT-423060-02 Ordering Information Table 31 lists the CYBT-4230xx-02 part numbers and features. Table 31 also lists the target program for the respective module ordering codes. Table 32 lists the reel shipment quantities for CYBT-4230xx-02. Table 31. Ordering Information Ordering Part Number CYBT-423054-02 CYBT-423060-02 Max CPU Flash Main Chip Part Number Speed Size RAM Size UART I2C SPI (MHz) (KB) (KB) CYW20719B2KUMLG 96 1024 512 Yes Yes Yes CYW20721B2KUMLG 96 1024 512 Yes Yes Yes I2S PCM PWM ADC Inputs GPIOs Package Packaging Yes Yes 6 11 17 28-SMT Tape and Reel Yes Yes 6 11 17 28-SMT Tape and Reel Table 32. Tape and Reel Package Quantity and Minimum Order Amount Description Reel Quantity Minimum Order Quantity (MOQ) Order Increment (OI) Minimum Reel Quantity 500 500 500 Maximum Reel Quantity Comments 500 Ships in 500 unit reel quantities. CYBT-4230xx-02 is offered in tape and reel packaging. CYBT-4230xx-02 ships in a reel size of 500 units. For additional information and a complete list of Cypress Semiconductor Bluetooth products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. U.S. Cypress Headquarters Address U.S. Cypress Headquarter Contact Info Cypress website address 198 Champion Court, San Jose, CA 95134 (408) 943-2600 http://www.cypress.com Document Number: 002-30912 Rev. *A Page 45 of 48 CYBT-423054-02/CYBT-423060-02 Acronyms Table 33. Acronyms Used in this Document Acronym Description BLE Bluetooth Low Energy Bluetooth SIG Bluetooth Special Interest Group CE European Conformity CSA Canadian Standards Association EMI electromagnetic interference ESD electrostatic discharge FCC Federal Communications Commission GPIO general-purpose input/output ISED Innovation, Science and Economic Development (Canada) IDE integrated design environment KC Korea Certification MIC Ministry of Internal Affairs and Communications (Japan) OTA Over-the-Air PCB printed circuit board RX receive QDID qualification design ID SMT surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs TCPWM timer, counter, pulse width modulator (PWM) TUV Germany: Technischer Überwachungs-Verein (Technical Inspection Association) TX transmit Document Conventions Units of Measure Table 34. Units of Measure Symbol °C Unit of Measure degree Celsius kV kilovolt mA milliamperes mm millimeters mV millivolt A microamperes m micrometers MHz megahertz GHz V gigahertz volt Document Number: 002-30912 Rev. *A Page 46 of 48 CYBT-423054-02/CYBT-423060-02 Document History Page Document Title: CYBT-423054-02/CYBT-423060-02, EZ-BTTM WICED® Module Document Number: 002-30912 Revision ECN Submission Date Description of Change ** 6870573 07/28/2020 Initial release. *A 7047618 12/17/2020 Replaced "Bluetooth Low Energy (BLE)" with "Bluetooth Low Energy" in all instances across the document. Replaced "BLE" with "Bluetooth LE" in all instances across the document. Document Number: 002-30912 Rev. *A Page 47 of 48 CYBT-423054-02/CYBT-423060-02 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. 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"High-Risk Device" means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-30912 Rev. *A Revised December 17, 2020 Page 48 of 48Adobe Acrobat Pro 10.1.16