AN-PS0008-Coolset F3 Latch Jitter design guide V1 1

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Document DEVICE REPORTInfineon-Design guide integrated power stage CoolSET F3 latch and jitter version-AN-v01 01-EN

Application Note, V1.1, October 2009
ICE3Axx65LJ/ICE3Bxx65LJ
CoolSETTM F3 Latch & Jitter version Design Guide
Power Management & Supply
Never stop thinking.

Edition 2009-10-31 Published by Infineon Technologies Asia Pacific, 168 Kallang Way, 349253 Singapore, Singapore © Infineon Technologies AP 2004. All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.
Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com).
Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

ICE3AXX65LJ/ 3BXX65LJ

Revision History: Previous Version: Page 8

2009-10 V1.0 Subjects (major changes since last revision) Add precaution for the start up sequence.

V1.1

CoolSETTM F3 Latch & Jitter version Design Guide: License to Infineon Technologies Asia Pacific Pte Ltd
Kok Siu Kam Eric Jeoh Meng Kiat
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected]

AN-PS0008

ICE3AXX65LJ/ ICE3BXX65LJ

Table of Contents

Page

1
2
3
4
5
6 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.4 6.5 6.6 6.6.1 6.6.2 6.6.3
7
8
9

Introduction ...................................................................................................................................5
List of Features .............................................................................................................................5
Package ..........................................................................................................................................5
Block Diagram ...............................................................................................................................6
Typical Application Circuit...........................................................................................................7
Function Description ....................................................................................................................8 Startup Cell......................................................................................................................................8 Soft Start and Normal Operation.....................................................................................................8 Active Burst Mode ...........................................................................................................................9 Entering Active Burst Mode.............................................................................................................9 Working in Active Burst Mode .......................................................................................................10 Leaving Active Burst Mode ...........................................................................................................11 VCC supply during burst mode .......................................................................................................12 Switching frequency modulation ...................................................................................................12 Propagation delay compensation..................................................................................................13 Protection Features .......................................................................................................................13 Auto Restart Mode ........................................................................................................................14 Latched Off Mode..........................................................................................................................14 Blanking Time for over load protection .........................................................................................15
Layout Recommendation ...........................................................................................................16
CoolSETTM F3 Latch & Jitter version Table ..............................................................................16
References ...................................................................................................................................16

Application Note

2009-10-31

ICE3AXX65LJ/ ICE3BXX65LJ

Introduction

The ICE3A(B)xx65LJ is the further development of the third generation CoolSETTM-F3. It is a PWM controller with power MOSFET together in a DIP-8 package. The switching frequency is running at 100(67) KHz and it targets for DVD player, set-top box, portable game console, auxiliary power supply, etc.
The ICE3A(B)xx65LJ adopts the BICMOS technology and provides a wider Vcc operating range up to 26V. It inherits the proven good features of CoolSETTM-F3 such as the active burst mode achieving the lowest standby power, the propagation delay compensation making the most precise current limit control in wide input voltage range, etc. In addition, it also adds on some useful features such as built-in soft start time, builtin basic with extendable blanking time for over load protection and built-in switching frequency modulation ( frequency jittering ), latch off enable pin, etc.
In this application note, functions of the device are described in detail with formula and its performance is shown with the test waveforms. The description of other related information such as DCM/CCM mode operating principles and slope compensation and the detailed design procedure are shown in the application note "AN-SMPS-ICE2xXXX-1".

List of Features

650V avalanche rugged CoolMOSTM with built in switchable Startup Cell Active Burst Mode for lowest Standby Power BiCMOS technology provide wide Vcc voltage range Fast load jump response in Active Burst Mode 100kHz fixed switching frequency with frequency modulation Latched Off mode for over temperature, Vcc over voltage and short winding protection Auto Restart Mode for over load protection, Open Loop protection and Vcc under voltage protection Built-in soft start time Built-in and extendable blanking window for short duration peak current External latch off enable pin Propagation delay compensation provides accurate primary current limit Switching frequency modulation and soft gate driving for low EMI

Package

The package for CoolSETTM-F3 Latch and Jitter mode product is DIP-8.

SoftS

GND

VCC

Drain

Figure 1 DIP-8 package

Application Note

2009-10-31

Block Diagram

ICE3AXX65LJ/ ICE3BXX65LJ

Figure 2 Block Diagram of CoolSETTM-F3 ICE3XXX65LJ

Application Note

2009-10-31

Typical Application Circuit

Figure 3 Typical application circuit with CoolSETTM-F3, ICE3A1065LJ 15W 5V

Application Note

F1 0.1uF/275V L1

3.15A

85V - 265Vac

EMI

N
2 x 27mH, 0.5A

BR1 2KBB80R

C4 2.2nF/250V, Y1

C23 * R21 *

TR1

D21 MBR745

L21 1.5uH

+ C2

R1 150k/2W

66T C3
2n2F/400V

47uF/400V

3 9

UF4005

+ C21 2200uF/35V

5V/3.0A
+ C22
470uF/35V
GND

ICE3AXX65LJ/ ICE3BXX65LJ

R4A

1.2R

27R

DRAI N DRAIN

C7 #

1 6 BL

IC1 ICE3A1065LJ

2
13T C5 22u/25V
D2 1
R2 1N4148 Lp=520uH 510R

GND

Vcc

Rc5

Rc6

Cc2 1nF

1 100R

C6 39R

1nF 0.1u

ZD1 22V

IC2 SFH617A-3

Rc4 6.8k
IC3 TL431

Rc1 10k
Cc1 Rc2 1uF 0R

Rc3A Rc3

10k

15W 5V SMPS Demoboard with ICE3A1065LJ
Eric Kok /18 Sep 06

2009-10-31

ICE3AXX65LJ/ ICE3BXX65LJ

Function Description

6.1

Startup Cell

The Startup Cell delivers a constant charge current of IVCCCharge=0.9mA to charge up the VCC capacitor CVcc at VCC pin. When VCC exceeds the on-threshold VCCon=18V, the bias circuit is switched on. The Startup Cell is switched off by UVLO for reducing the power loss. The startup delay time, tDELAY, is independent from the AC line input voltage. It can be estimated by the equation (1):

t = I V - CI DELAY

VCCon Vcc _ Ch arg e

Vcc Vcc _ Start

(1)

where, IVcc_Start is the supply current when IC is in off state. Figure 4 shows the startup time delay at 85VAC input. ( Pls refer to the datasheet for the symbol used in the equation )

0.6s

Figure 4 The startup delay time at AC line input voltage of 85V.
Precaution : For a typical application, start up should be VCC ramps up first, other pin (such as FB pin) voltage will follow VCC voltage to ramp up. It is recommended not to have any voltage on other pins (such as FB; BA and CS) before VCC ramps up.

6.2

Soft Start and Normal Operation

When the IC is turned on after the Startup Delay time, a digital soft start circuit is activated. A gradually increased soft start voltage is emitted by the digital soft start circuit, which in turn increases the duty cycle accordingly. The soft start control voltage is increased with the increasing of count number in the digital counter of the soft start circuit. The soft start time is set at 20ms. When the soft start time ends, IC goes into normal mode and the duty cycle is dependent on the FB signal. Figure 5 shows the soft start behaviour at 85VAC input. It can be seen that the primary peak current slowly increase to the maximum in the soft start period. After soft start stage, IC goes into normal operation with the conventional primary peak current control scheme. Please refer to "AN-SMPS-ICE2xXXXX-1" for the details of normal operation.

Application Note

2009-10-31

ICE3AXX65LJ/ ICE3BXX65LJ

20ms

Figure 5 Soft start at AC line input voltage of 85V

6.3

Active Burst Mode

The IC provides an Active Burst Mode function at no load or low load conditions to enable the system to achieve the lowest standby power requirement of less than 100mW. Active Burst Mode means the IC is always in the active state and can therefore immediately response to any changes on the FB signal, VFB.

6.3.1 Entering Active Burst Mode

Because of the current mode control scheme, the feedback voltage VFB actually controls the power delivery to output. When the output load is getting lower, the feedback voltage VFB drops. If it stays below 1.35V for a pre-set time frame of 20ms, the IC enters into the burst mode operation. The threshold power to enter burst
mode is:

PBURST _ enter

= 0.5 LP

(VFBC5 - VOffset-Ramp ) 2 Rsense AV

f SW

(2)

where, LP is the transformer primary inductance, VFBC5=1.35V is the feedback voltage at which the system starts to burst, VOffset-Ramp=0.6V is the maximum level of the internal Voltage Ramp on which the amplified current ramp signal of the PWM-OP is superimposed, AV =3.2 is the internal PWM-OP gain, Rsense is the current sense resistor, fSW is the switching frequency. Figure 6 shows the test waveform with the load drop from full load to light load. After blanking time IC goes into burst mode.

Application Note

2009-10-31

ICE3AXX65LJ/ ICE3BXX65LJ

19.3ms

Figure 6 Entering Burst Mode

6.3.2 Working in Active Burst Mode

During active burst mode, the IC is constantly monitoring the output voltage by feedback pin, VFB, which controls burst duty cycle and burst frequency. The burst "on" starts when VFB reaches 3.61V and stops when VFB is down to 3.0V. During burst "on", the primary current limit is set to only 31% of maximum peak current (VCS=0.31V) to reduce the conduction losses and to avoid audible noise. The FB voltage is changing like a saw tooth between 3.0V and 3.61V.The corresponding secondary output ripple (peak to peak) is regulated
as below:

Vout _ ripple _ pp

RFB

Ropto Gopto GTL431

VFB

(3)

where, Ropto is the resistor in series with opto-coupler at the secondary side to limit the opto-coupler current, RFB is the IC internal pull up resistor connected to FB Pin ( refer to Figure 2 ), Gopto is the current transfer gain of opto-coupler, GTL431 is the voltage transfer gain between the comparator TL431 output and Vout, VFB=3.61-3.0=0.61V is the ripple on the VFB during burst operation.
The leaving burst power threshold, i.e. maximum power to be handled during burst operation is:

Pburst _ max

= 0.5 LP (0.31 i peak _ max ) 2

f SW

0.5

(0.31 VCS _ max Rsense

f SW

= 0.0961 Pmax

(4)

Where, ipeak_max is the maximum primary peak current, VCS_max is the cycle by cycle current limit threshold at CS pin, Pmax is the maximum output power of the power supply. It can be seen that the maximum power in burst mode is around 9.61% of Pmax. Figure 7 shows the test waveform of burst mode at light load. It can be seen that the burst ripple is well regulated to be 40mV and it is independent on the output power.

Application Note

2009-10-31

ICE3AXX65LJ/ ICE3BXX65LJ

40mV

Figure 7 working in Burst Mode at light load
6.3.3 Leaving Active Burst Mode
When the output load is increasing to be higher than Pburst_max, Vout will drop a little bit and VFB will rise up fast to 4.5V. The system leaves burst mode immediately when VFB reaches 4.5V. Once system leaves burst mode, the current sense voltage limit, VCS_MAX, is released to 1V, the feedback voltage VFB swings back to the required level. The timing diagram of leaving burst mode is shown in Figure 8.
4.5V 3.61V
VFB
3.0V

Vout Vout_AV

Vout_drop_max

VCS 0.31V
Figure 8 the timing diagram of leaving burst mode

The maximum Vout drop during the mode transition is

Vout _ drop _ max

RFB

Ropto Gopto GTL431

(4.5 -

3.0 + 3.61) 2

1.195 Ropto RFB Gopto GTL431

Application Note

(5) 2009-10-31

ICE3AXX65LJ/ ICE3BXX65LJ
Figure 9 shows the waveform to leave burst mode with load jump from light load to full load. The output voltage drop during the transition is about 140mV.
140mV

Figure 9 test waveform of leaving burst mode

6.3.4 VCC supply during burst mode
The supply voltage for VCC has to be designed so that it always stays above VVCCoff limit during burst mode, even at no load. This can lead to a substantial high voltage at VCC pin during maximum load operation. The circuit configuration for VCC in Figure 3, which consists of C5, R2, R3, ZD1 and C6, is to ensure that the VCC will never exceed 26V under any operation conditions.

6.4

Switching frequency modulation

The IC is running at fixed frequency of 100KHz with jittering frequency at +/-4KHz in a switching modulation period of 4ms. This kind of frequency modulation can effectively help to obtain a low noise level conduction EMI measurement. The measurement jittering frequency is 96.2KHz ~ 103.5KHz ( Figure 10 ).

96.2KHz 103.5KHz

Figure 10 Switching frequency jittering

Application Note

2009-10-31

ICE3AXX65LJ/ ICE3BXX65LJ

6.5

Propagation delay compensation

It is observed that the maximum input power will change with input voltage. This is due to the propagation delay of the controller in different dI/dt of the input voltage. The power difference can be as high as >14% between high line and low line. Starting from our 2nd generation, a propagation delay compensation network is implemented so that the power difference is greatly reduced to best around 2%. A measured result for a 15W demo boards shows an output power difference of around +/-3.8% between 85Vac and 269 Vac input. Figure 11 shows the propagation delay compensation curve implemented to the IC. This function applies to discontinuous conduction mode flyback converter only.

Sense V

V
1,3 1,25
1,2 1,15
1,1 1,05
1 0,95
0,9 0

with compensation

without compensation

0,2 0,4 0,6 0,8

1 1,2 1,4 1,6 1,8
dVSense dt

2V µs

Figure 11 Propagation delay compensation curve

6.6

Protection Features

The IC provides several protection features which lead to the Auto Restart Mode or Latched off mode. The following table shows the conditions of the system failure and the associate protection mode.

Protection functions

Failure condition

VCC Over voltage
Over temperature ( controller ) Short Winding/ Short Diode BL pin < 0.1V ( BL is external latch enable pin ) Output Overload / Output Short Circuit

VCC > 24V and VFB > 4.5V TJ > 130OC
VCS>1.66V
VBL<0.1V VFB > 4.5V and VBL > 4.0V ( after built-in / extended blanking time )

Open Loop

-> Output Over Load

VCC Undervoltage / short Opto-coupler

VCC < 10.5V

Protection Mode Latched off Latched off Latched off Latched off Auto Restart Auto Restart Auto Restart

Application Note

2009-10-31

ICE3AXX65LJ/ ICE3BXX65LJ
6.6.1 Auto Restart Mode
There is always a startup phase with switching cycles in the Auto Restart Mode. After this startup phase the conditions are checked whether the failure is still present. Normal operation proceeds once the failure mode is removed. Otherwise, new startup phase will be initiated again. Figure 12 shows the switching waveform of the VCC and the feedback voltage VFB when the output is shorted to ground. The IC is turned on at VCC = 18V. After going through the startup phase, IC is off again due to the fault still exists. VCC is discharged until 10.5V. Then, the Startup Cell is activated again to charge up capacitor at VCC that initiates another restart cycle.

Figure 12 Auto Restart Mode ( without extended blanking time )
6.6.2 Latched Off Mode
In case of Latched Off Mode, there is no new startup phase any more. Once Latched Off Mode is entered, the internal Voltage Reference is switched off in order to reduce the current consumption of the IC. In this stage only the UVLO is working which switches on/off the startup cell at VCCoff/VCCon. Latched Off Mode can only be reset when AC line input is plugged out and VCC is discharged to be lower than 6.23V.

Figure 13 Latch off Mode ( VBL < 0.1V )

Application Note

2009-10-31

ICE3AXX65LJ/ ICE3BXX65LJ

6.6.3 Blanking Time for over load protection

The IC controller provides a blanking window before entering into the auto restart mode due to output overload/short circuit. The purpose is to ensure that the system will not enter protection mode unintentionally. There are 2 kinds of the blanking time; basic and the extendable. The basic one is a built-in feature which is set at 20ms. The extendable one is to extend the basic one with a user defined additional blanking time. The extendable blanking time can be achieved by adding a capacitor, CBK to the BL pin. When there is over load occurred ( VFB > 4.5V ), the CBK capacitor will be charged up by an constant current source, IBK ( 8.4uA ) from 0.9V to 4.0V. Then the auto restart protection will be activated. The charging time from 0.9V to 4.0V to the CBK capacitor is the extended blanking time. The total blanking time is the addition of the basic and the extended blanking time.

Tblanking = Basic + Extended = 20ms + (4.0 - 0.9) * CBK = 20ms + 369047.6 * CBK

IBK

The measured total blanking time showing in figure 14 is 125ms using CBK=0.22uF.

In case of output overload or short circuit, the transferred power during the blanking period is limited to the maximum power defined by the value of the sense resistor Rsense.

20ms

Figure 14 blanking window for output over load protection ( basic blanking time )

20ms

105ms

Figure 15 blanking window for output overload protection ( with extended blanking time, CBK=0.22uF )

Application Note

2009-10-31

ICE3AXX65LJ/ ICE3BXX65LJ

Layout Recommendation

In order to get the optimized performance of the CoolSETTM, the grounding of the PCB layout must be connected carefully. From the circuit diagram in figure 7, it indicates that the grounding for the CoolSETTM can be split into several groups; signal ground, Vcc ground, Current sense resistor ground and EMI return ground. All the split grounds should be "star" connected to the bulk capacitor ground directly. The split grounds are described as below.
· Signal ground includes all small signal grounds connecting to the CoolSETTM GND pin such as filter capacitor ground, C6, C7, C8 and opto-coupler ground.

· Vcc ground includes the Vcc capctior ground, C5 and the auxiliary winding ground, pin 2 of the power transformer.

· Current Sense resistor ground includes current sense resistor R4 and R4A.

· EMI return ground includes Y capacitor, C4.

CoolSETTM F3 Latch & Jitter version Table

Device

Package

VDS

Current /A Rdson /1

ICE3A1065LJ PG-DIP-8 650V

1.0

2.95

Frequency / KHz
100

Pout @ 230Vac±15%2
32W

Pout @ 85-265Vac 2 16W

References

[1] Infineon Technologies, Datasheet "CoolSETTM-F3 ICE3A1065LJ Off-Line SMPS Current Mode Controller with Integrated 650V Startup Cell / CoolMOSTM ( Latched and Frequency Jitter Mode )"
[2] Eric Kok Siu Kam, Jeoh Meng Kiat, Infineon Technologies, Application Note "AN-EVALSF3ICE3A1065LJ, 15W 5.0V SMPS Evaluation Board with CoolSETTM F3 ICE3A1065LJ "
[3] Harald Zoellinger, Rainer Kling, Infineon Technologies, Application Note "AN-SMPS-ICE2xXXX-1, CoolSETTM ICE2xXXXX for Off-Line Switching Mode Power supply (SMPS )"

1 Typ @ 25°C 2 Calculated maximum input power rating at Ta=75°C, Tj=125°C and without copper area as heat sink.

Application Note

2009-10-31

Acrobat Distiller 5.0.5 (Windows)